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Searched refs:NBITS (Results 1 – 25 of 38) sorted by relevance

/external/llvm-project/llvm/test/Transforms/InstCombine/
D	redundant-right-shift-input-masking.ll	15 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 17 ; CHECK-NEXT: [[T2:%.]] = lshr exact i32 [[T1]], [[NBITS]] 27 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 29 ; CHECK-NEXT: [[T2:%.]] = ashr exact i32 [[T1]], [[NBITS]] 42 ; CHECK-NEXT: [[T0:%.]] = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 44 ; CHECK-NEXT: [[T2:%.]] = lshr <4 x i32> [[T1]], [[NBITS]] 55 ; CHECK-NEXT: [[T0:%.]] = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.]] 57 ; CHECK-NEXT: [[T2:%.]] = lshr <4 x i32> [[T1]], [[NBITS]] 72 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 75 ; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]] [all …]
D	redundant-left-shift-input-masking-variant-f.ll	20 ; CHECK-NEXT: [[T0:%.]] = shl i32 [[X:%.]], [[NBITS:%.]] 21 ; CHECK-NEXT: [[T1:%.]] = ashr i32 [[T0]], [[NBITS]] 24 ; CHECK-NEXT: [[T2:%.]] = shl i32 [[X]], [[NBITS]] 37 ; CHECK-NEXT: [[T0:%.]] = shl i32 [[X:%.]], [[NBITS:%.]] 38 ; CHECK-NEXT: [[T1:%.]] = ashr i32 [[T0]], [[NBITS]] 39 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], 1 62 ; CHECK-NEXT: [[T0:%.]] = shl <3 x i32> [[X:%.]], [[NBITS:%.]] 63 ; CHECK-NEXT: [[T1:%.]] = ashr <3 x i32> [[T0]], [[NBITS]] 64 ; CHECK-NEXT: [[T2:%.]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1> 83 ; CHECK-NEXT: [[T0:%.]] = shl <3 x i32> [[X:%.]], [[NBITS:%.]] [all …]
D	redundant-left-shift-input-masking-variant-e.ll	20 ; CHECK-NEXT: [[T0:%.]] = shl i32 [[X:%.]], [[NBITS:%.]] 21 ; CHECK-NEXT: [[T1:%.]] = lshr i32 [[T0]], [[NBITS]] 24 ; CHECK-NEXT: [[T2:%.]] = shl i32 [[X]], [[NBITS]] 37 ; CHECK-NEXT: [[T0:%.]] = shl i32 [[X:%.]], [[NBITS:%.]] 38 ; CHECK-NEXT: [[T1:%.]] = lshr i32 [[T0]], [[NBITS]] 39 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], 1 62 ; CHECK-NEXT: [[T0:%.]] = shl <3 x i32> [[X:%.]], [[NBITS:%.]] 63 ; CHECK-NEXT: [[T1:%.]] = lshr <3 x i32> [[T0]], [[NBITS]] 64 ; CHECK-NEXT: [[T2:%.]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1> 83 ; CHECK-NEXT: [[T0:%.]] = shl <3 x i32> [[X:%.]], [[NBITS:%.]] [all …]
D	partally-redundant-left-shift-input-masking-variant-d.ll	18 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 19 ; CHECK-NEXT: [[T1:%.]] = lshr i32 [[T0]], [[NBITS]] 20 ; CHECK-NEXT: [[T3:%.]] = add i32 [[NBITS]], -1 45 …]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 46 ; CHECK-NEXT: [[T1:%.]] = lshr <8 x i32> [[T0]], [[NBITS]] 47 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32… 68 … = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.]] 69 ; CHECK-NEXT: [[T1:%.]] = lshr <8 x i32> [[T0]], [[NBITS]] 70 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32… 91 …]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]] [all …]
D	set-lowbits-mask-canonicalize.ll	20 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 31 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 62 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 73 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 104 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 115 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 146 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 157 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw i32 -1, [[NBITS:%.]] 190 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw <2 x i32> <i32 -1, i32 -1>, [[NBITS:%.]] 201 ; CHECK-NEXT: [[NOTMASK:%.]] = shl nsw <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] [all …]
D	redundant-left-shift-input-masking-variant-d.ll	20 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 21 ; CHECK-NEXT: [[T1:%.]] = lshr i32 [[T0]], [[NBITS]] 26 ; CHECK-NEXT: [[T4:%.]] = shl i32 [[X]], [[NBITS]] 41 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 42 ; CHECK-NEXT: [[T1:%.]] = lshr i32 [[T0]], [[NBITS]] 44 ; CHECK-NEXT: [[T3:%.]] = add i32 [[NBITS]], 1 70 ; CHECK-NEXT: [[T0:%.]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 71 ; CHECK-NEXT: [[T1:%.]] = lshr <3 x i32> [[T0]], [[NBITS]] 73 ; CHECK-NEXT: [[T3:%.]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1> 95 ; CHECK-NEXT: [[T0:%.]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] [all …]
D	redundant-left-shift-input-masking-variant-c.ll	20 ; CHECK-NEXT: [[T0:%.]] = lshr i32 -1, [[NBITS:%.]] 24 ; CHECK-NEXT: [[T2:%.]] = shl i32 [[X]], [[NBITS]] 37 ; CHECK-NEXT: [[T0:%.]] = lshr i32 -1, [[NBITS:%.]] 39 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], 1 62 ; CHECK-NEXT: [[T0:%.]] = lshr <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 64 ; CHECK-NEXT: [[T2:%.]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1> 83 ; CHECK-NEXT: [[T0:%.]] = lshr <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 85 ; CHECK-NEXT: [[T2:%.]] = add <3 x i32> [[NBITS]], <i32 1, i32 0, i32 2> 104 ; CHECK-NEXT: [[T0:%.]] = lshr <3 x i32> <i32 -1, i32 undef, i32 -1>, [[NBITS:%.]] 106 ; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 undef, i32 1> [all …]
D	partally-redundant-left-shift-input-masking-variant-e.ll	18 ; CHECK-NEXT: [[T0:%.]] = shl i32 [[X:%.]], [[NBITS:%.]] 19 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -1 41 ; CHECK-NEXT: [[T0:%.]] = shl <8 x i32> [[X:%.]], [[NBITS:%.]] 42 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32… 60 ; CHECK-NEXT: [[T0:%.]] = shl <8 x i32> [[X:%.]], [[NBITS:%.]] 61 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32… 79 ; CHECK-NEXT: [[T0:%.]] = shl <8 x i32> [[X:%.]], [[NBITS:%.]] 80 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32… 100 ; CHECK-NEXT: [[T0:%.]] = shl i32 [[X:%.]], [[NBITS:%.]] 101 ; CHECK-NEXT: [[T1:%.]] = lshr i32 [[T0]], [[NBITS]] [all …]
D	redundant-left-shift-input-masking-variant-a.ll	20 ; CHECK-NEXT: [[T0:%.]] = shl i32 1, [[NBITS:%.]] 23 ; CHECK-NEXT: [[T3:%.]] = sub i32 32, [[NBITS]] 45 ; CHECK-NEXT: [[T0:%.]] = shl i32 1, [[NBITS:%.]] 48 ; CHECK-NEXT: [[T3:%.]] = sub i32 33, [[NBITS]] 70 ; CHECK-NEXT: [[T0:%.]] = add i32 [[NBITS:%.]], 1 74 ; CHECK-NEXT: [[T4:%.]] = sub i32 32, [[NBITS]] 103 ; CHECK-NEXT: [[T1:%.]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[NBITS:%.]] 106 ; CHECK-NEXT: [[T4:%.]] = sub <3 x i32> <i32 32, i32 32, i32 32>, [[NBITS]] 107 ; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]]) 131 ; CHECK-NEXT: [[T0:%.]] = add <3 x i32> [[NBITS:%.]], <i32 -1, i32 0, i32 1> [all …]
D	partally-redundant-left-shift-input-masking-variant-c.ll	18 ; CHECK-NEXT: [[T0:%.]] = lshr i32 -1, [[NBITS:%.]] 19 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -1 41 …]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 42 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32… 60 …= lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.]] 61 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32… 79 …]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 80 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32… 100 ; CHECK-NEXT: [[T0:%.]] = lshr i32 -1, [[NBITS:%.]] 102 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -1
D	redundant-left-shift-input-masking-after-truncation-variant-b.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 22 ; CHECK-NEXT: [[T3:%.]] = sub i32 32, [[NBITS]] 24 ; CHECK-NEXT: call void @use32(i32 [[NBITS]]) 59 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 62 …3:%.]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]] 64 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]]) 94 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 97 ….]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]] 99 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]]) 129 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 0, i32 0, i32 1, i32 0, i32… [all …]
D	redundant-left-shift-input-masking-variant-b.ll	20 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 23 ; CHECK-NEXT: [[T3:%.]] = sub i32 32, [[NBITS]] 45 ; CHECK-NEXT: [[T0:%.]] = shl i32 -1, [[NBITS:%.]] 48 ; CHECK-NEXT: [[T3:%.]] = sub i32 33, [[NBITS]] 70 ; CHECK-NEXT: [[T0:%.]] = add i32 [[NBITS:%.]], 1 74 ; CHECK-NEXT: [[T4:%.]] = sub i32 32, [[NBITS]] 103 ; CHECK-NEXT: [[T1:%.]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.]] 106 ; CHECK-NEXT: [[T4:%.]] = sub <3 x i32> <i32 32, i32 32, i32 32>, [[NBITS]] 107 ; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]]) 131 ; CHECK-NEXT: [[T0:%.]] = add <3 x i32> [[NBITS:%.]], <i32 -1, i32 0, i32 1> [all …]
D	redundant-left-shift-input-masking-after-truncation-variant-a.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 22 ; CHECK-NEXT: [[T3:%.]] = sub i32 32, [[NBITS]] 24 ; CHECK-NEXT: call void @use32(i32 [[NBITS]]) 59 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 62 …3:%.]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]] 64 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]]) 94 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 97 ….]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]] 99 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]]) 129 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64> [all …]
D	conditional-variable-length-signext-after-high-bit-extract.ll	19 ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.]] = sub i32 32, [[NBITS:%.]] 22 ; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.]] = shl i32 -1, [[NBITS]] 50 ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.]] = sub i32 32, [[NBITS:%.]] 53 ; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.]] = shl i32 -1, [[NBITS]] 81 ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.]] = sub i32 32, [[NBITS:%.]] 84 ; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.]] = shl i32 1, [[NBITS]] 112 ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.]] = sub i32 64, [[NBITS:%.]] 117 ; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.]] = shl i32 -1, [[NBITS]] 149 ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.]] = sub i32 64, [[NBITS:%.]] 154 ; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl i32 -1, [[NBITS]] [all …]
D	variable-signext-of-variable-high-bit-extraction.ll	10 ; CHECK-NEXT: [[SKIP_HIGH:%.]] = sub i32 64, [[NBITS:%.]] 18 ; CHECK-NEXT: [[NUM_HIGH_BITS_TO_SMEAR_NARROW:%.]] = sub i32 32, [[NBITS]] 40 ; CHECK-NEXT: [[NBITS:%.]] = zext i8 [[NBITS_NARROW:%.]] to i16 41 ; CHECK-NEXT: call void @use16(i16 [[NBITS]]) 42 ; CHECK-NEXT: [[SKIP_HIGH:%.]] = sub nsw i16 64, [[NBITS]] 50 ; CHECK-NEXT: [[NUM_HIGH_BITS_TO_SMEAR_NARROW_NARROW:%.]] = sub nsw i16 32, [[NBITS]] 78 ; CHECK-NEXT: [[SKIP_HIGH:%.]] = sub i32 64, [[NBITS:%.]] 86 ; CHECK-NEXT: [[NUM_HIGH_BITS_TO_SMEAR_NARROW:%.]] = sub i32 32, [[NBITS]] 109 ; CHECK-NEXT: [[SKIP_HIGH:%.]] = sub i32 64, [[NBITS:%.]] 117 ; CHECK-NEXT: [[NUM_HIGH_BITS_TO_SMEAR_NARROW:%.*]] = sub i32 32, [[NBITS]] [all …]
D	partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 21 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -33 51 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 53 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33… 78 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 80 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33… 105 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 107 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -64, i32 -63, i32 -33, i32 -32, i32 63,… 134 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 136 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33 [all …]
D	partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 21 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -33 51 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 53 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33… 78 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 80 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33… 105 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 107 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -64, i32 -63, i32 -33, i32 -32, i32 63,… 134 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 136 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33 [all …]
D	redundant-left-shift-input-masking-after-truncation-variant-f.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 21 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -32 53 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 55 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 82 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 84 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 111 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 113 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -1, i32 0, i32 1, i32 31, i32 … 142 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 144 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -32 [all …]
D	sign-bit-test-via-right-shifting-all-other-bits.ll	9 ; CHECK-NEXT: [[NUM_LOW_BITS_TO_SKIP:%.]] = sub i32 32, [[NBITS:%.]] 11 ; CHECK-NEXT: [[SKIP_ALL_BITS_TILL_SIGNBIT:%.]] = add i32 [[NBITS]], -1 36 ; CHECK-NEXT: [[NUM_LOW_BITS_TO_SKIP:%.]] = sub i32 64, [[NBITS:%.]] 40 ; CHECK-NEXT: [[SKIP_ALL_BITS_TILL_SIGNBIT:%.]] = add i32 [[NBITS]], -1 71 ; CHECK-NEXT: [[NUM_LOW_BITS_TO_SKIP:%.]] = sub i32 32, [[NBITS:%.]] 73 ; CHECK-NEXT: [[SKIP_ALL_BITS_TILL_SIGNBIT:%.]] = add i32 [[NBITS]], -1 98 ; CHECK-NEXT: [[NUM_LOW_BITS_TO_SKIP:%.]] = sub i32 64, [[NBITS:%.]] 102 ; CHECK-NEXT: [[SKIP_ALL_BITS_TILL_SIGNBIT:%.]] = add i32 [[NBITS]], -1 133 ; CHECK-NEXT: [[NUM_LOW_BITS_TO_SKIP:%.]] = sub i32 32, [[NBITS:%.]] 135 ; CHECK-NEXT: [[SKIP_ALL_BITS_TILL_SIGNBIT:%.*]] = add i32 [[NBITS]], -1 [all …]
D	redundant-left-shift-input-masking-after-truncation-variant-e.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 21 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -32 53 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 55 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 82 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 84 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 111 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 113 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -1, i32 0, i32 1, i32 31, i32 … 142 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 144 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -32
D	redundant-left-shift-input-masking-after-truncation-variant-c.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 21 ; CHECK-NEXT: [[T2:%.]] = add i32 [[NBITS]], -32 53 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 55 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 82 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 84 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 111 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 113 ; CHECK-NEXT: [[T2:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -1, i32 0, i32 1, i32 31, i32 … 142 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 144 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -32
D	partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 22 ; CHECK-NEXT: [[T3:%.]] = add i32 [[NBITS]], -33 55 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 58 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33… 86 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 89 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33… 117 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 120 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -64, i32 -63, i32 -33, i32 -32, i32 63,… 150 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 153 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS]], -33 [all …]
D	partally-redundant-left-shift-input-masking-variant-b.ll	18 ; CHECK-NEXT: [[T0:%.]] = add i32 [[NBITS:%.]], -1 21 ; CHECK-NEXT: [[T4:%.]] = sub i32 32, [[NBITS]] 49 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1,… 52 …4:%.]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]] 76 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1,… 79 ….]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]] 103 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 … 106 …4:%.]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]] 132 ; CHECK-NEXT: [[T0:%.]] = add i32 [[NBITS:%.]], -1 136 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
D	partally-redundant-left-shift-input-masking-variant-a.ll	18 ; CHECK-NEXT: [[T0:%.]] = add i32 [[NBITS:%.]], -1 21 ; CHECK-NEXT: [[T4:%.]] = sub i32 32, [[NBITS]] 49 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1,… 52 …4:%.]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]] 76 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1,… 79 ….]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]] 103 ; CHECK-NEXT: [[T0:%.]] = add <8 x i32> [[NBITS:%.]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 … 106 …4:%.]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]] 132 ; CHECK-NEXT: [[T0:%.]] = add i32 [[NBITS:%.]], -1 136 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
D	redundant-left-shift-input-masking-after-truncation-variant-d.ll	19 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 22 ; CHECK-NEXT: [[T3:%.]] = add i32 [[NBITS]], -32 57 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 60 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 90 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 93 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -32, i32 -32, i32 -32, i32 -32… 123 ; CHECK-NEXT: [[T0:%.]] = zext <8 x i32> [[NBITS:%.]] to <8 x i64> 126 ; CHECK-NEXT: [[T3:%.]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -1, i32 0, i32 1, i32 31, i32 … 158 ; CHECK-NEXT: [[T0:%.]] = zext i32 [[NBITS:%.]] to i64 161 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS]], -32

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