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1 /*
2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NEOVERSE_E1_H
8 #define NEOVERSE_E1_H
9 
10 #include <lib/utils_def.h>
11 
12 #define NEOVERSE_E1_MIDR		U(0x410FD4A0)
13 
14 /*******************************************************************************
15  * CPU Extended Control register specific definitions.
16  ******************************************************************************/
17 #define NEOVERSE_E1_ECTLR_EL1		S3_0_C15_C1_4
18 
19 /*******************************************************************************
20  * CPU Auxiliary Control register specific definitions.
21  ******************************************************************************/
22 #define NEOVERSE_E1_CPUACTLR_EL1	S3_0_C15_C1_0
23 
24 /*******************************************************************************
25  * CPU Power Control register specific definitions.
26  ******************************************************************************/
27 
28 #define NEOVERSE_E1_CPUPWRCTLR_EL1				S3_0_C15_C2_7
29 #define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		(U(1) << 0)
30 
31 #endif /* NEOVERSE_E1_H */
32