| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/ |
| D | plat_memctrl.c | 38 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
39 mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE),
40 mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE),
41 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
42 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
43 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
44 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
45 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
47 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
48 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
[all …]
|
| /external/arm-trusted-firmware/services/spd/tspd/ |
| D | tspd_main.c | 67 ns_cpu_context = cm_get_context(NON_SECURE); in tspd_handle_sp_preemption()
80 cm_el1_sysregs_context_restore(NON_SECURE); in tspd_handle_sp_preemption()
81 cm_set_next_eret_context(NON_SECURE); in tspd_handle_sp_preemption()
105 assert(get_interrupt_src_ss(flags) == NON_SECURE); in tspd_sel1_interrupt_handler()
108 assert(handle == cm_get_context(NON_SECURE)); in tspd_sel1_interrupt_handler()
111 cm_el1_sysregs_context_save(NON_SECURE); in tspd_sel1_interrupt_handler()
345 ns_cpu_context = cm_get_context(NON_SECURE); in tspd_smc_handler()
353 cm_el1_sysregs_context_restore(NON_SECURE); in tspd_smc_handler()
354 cm_set_next_eret_context(NON_SECURE); in tspd_smc_handler()
388 set_interrupt_rm_flag(flags, NON_SECURE); in tspd_smc_handler()
[all …]
|
| /external/arm-trusted-firmware/bl32/sp_min/ |
| D | sp_min_main.c | 49 assert(security_state == NON_SECURE);
55 assert(security_state == NON_SECURE); in smc_set_next_ctx()
71 assert(security_state == NON_SECURE); in cm_get_context()
81 assert(security_state == NON_SECURE); in cm_set_context()
94 assert(security_state == NON_SECURE); in cm_get_context_by_index()
105 assert(security_state == NON_SECURE); in cm_set_context_by_index()
128 cpu_context_t *ctx = cm_get_context(NON_SECURE); in sp_min_prepare_next_image_entry()
134 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); in sp_min_prepare_next_image_entry()
139 smc_set_next_ctx(NON_SECURE); in sp_min_prepare_next_image_entry()
142 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), in sp_min_prepare_next_image_entry()
[all …]
|
| /external/arm-trusted-firmware/services/spd/tlkd/ |
| D | tlkd_main.c | 75 assert(get_interrupt_src_ss(flags) == NON_SECURE); in tlkd_interrupt_handler()
76 assert(handle == cm_get_context(NON_SECURE)); in tlkd_interrupt_handler()
79 cm_el1_sysregs_context_save(NON_SECURE); in tlkd_interrupt_handler()
141 set_interrupt_rm_flag(flags, NON_SECURE); in tlkd_setup()
237 ns_cpu_context = cm_get_context(NON_SECURE); in tlkd_smc_handler()
245 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_smc_handler()
246 cm_set_next_eret_context(NON_SECURE); in tlkd_smc_handler()
288 assert(handle == cm_get_context(NON_SECURE)); in tlkd_smc_handler()
303 cm_el1_sysregs_context_save(NON_SECURE); in tlkd_smc_handler()
384 ns_cpu_context = cm_get_context(NON_SECURE); in tlkd_smc_handler()
[all …]
|
| /external/arm-trusted-firmware/services/spd/opteed/ |
| D | opteed_main.c | 62 assert(get_interrupt_src_ss(flags) == NON_SECURE); in opteed_sel1_interrupt_handler()
65 assert(handle == cm_get_context(NON_SECURE)); in opteed_sel1_interrupt_handler()
68 cm_el1_sysregs_context_save(NON_SECURE); in opteed_sel1_interrupt_handler()
216 assert(handle == cm_get_context(NON_SECURE)); in opteed_smc_handler()
218 cm_el1_sysregs_context_save(NON_SECURE); in opteed_smc_handler()
301 set_interrupt_rm_flag(flags, NON_SECURE); in opteed_smc_handler()
367 ns_cpu_context = cm_get_context(NON_SECURE); in opteed_smc_handler()
371 cm_el1_sysregs_context_restore(NON_SECURE); in opteed_smc_handler()
372 cm_set_next_eret_context(NON_SECURE); in opteed_smc_handler()
382 ns_cpu_context = cm_get_context(NON_SECURE); in opteed_smc_handler()
[all …]
|
| /external/arm-trusted-firmware/services/spd/trusty/ |
| D | trusty.c | 100 ctx_smc = cm_get_context(NON_SECURE); in trusty_context_switch()
147 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0); in trusty_fiq_handler()
164 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr); in trusty_fiq_handler()
205 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0); in trusty_fiq_exit()
223 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr); in trusty_fiq_exit()
297 ret = trusty_context_switch(NON_SECURE, smc_fid, x1, in trusty_smc_handler()
321 fpregs_context_save(get_fpregs_ctx(cm_get_context(NON_SECURE))); in trusty_init()
322 cm_el1_sysregs_context_save(NON_SECURE); in trusty_init()
346 cm_el1_sysregs_context_restore(NON_SECURE); in trusty_init()
347 fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE))); in trusty_init()
[all …]
|
| /external/arm-trusted-firmware/bl1/ |
| D | bl1_fwu.c | 249 if (GET_SECURITY_STATE(desc->ep_info.h.attr) == NON_SECURE) { in bl1_fwu_image_copy()
520 (GET_SECURITY_STATE(desc->ep_info.h.attr) == NON_SECURE) || in bl1_fwu_image_execute()
531 cm_el1_sysregs_context_save(NON_SECURE); in bl1_fwu_image_execute()
562 if (caller_sec_state == NON_SECURE) { in bl1_fwu_image_resume()
581 resume_sec_state = NON_SECURE; in bl1_fwu_image_resume()
624 if (GET_SECURITY_STATE(flags) == NON_SECURE) { in bl1_fwu_sec_image_done()
655 cm_el1_sysregs_context_restore(NON_SECURE); in bl1_fwu_sec_image_done()
658 cm_set_next_eret_context(NON_SECURE); in bl1_fwu_sec_image_done()
660 *handle = cm_get_context(NON_SECURE); in bl1_fwu_sec_image_done()
663 cm_set_next_context(cm_get_context(NON_SECURE)); in bl1_fwu_sec_image_done()
[all …]
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_fiq_glue.c | 42 cpu_context_t *ctx = cm_get_context(NON_SECURE); in tegra_fiq_interrupt_handler()
60 cm_el1_sysregs_context_save(NON_SECURE); in tegra_fiq_interrupt_handler()
73 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr); in tegra_fiq_interrupt_handler()
129 cpu_context_t *ctx = cm_get_context(NON_SECURE); in tegra_fiq_get_intr_context()
|
| /external/arm-trusted-firmware/plat/arm/css/sgi/ |
| D | sgi_ras.c | 116 cm_el1_sysregs_context_save(NON_SECURE); in sgi_ras_intr_handler()
165 cm_el1_sysregs_context_restore(NON_SECURE); in sgi_ras_intr_handler()
166 cm_set_next_eret_context(NON_SECURE); in sgi_ras_intr_handler()
|
| /external/arm-trusted-firmware/plat/mediatek/mt6795/ |
| D | bl31_plat_setup.c | 159 next_image_info = (type == NON_SECURE) ? in bl31_plat_get_next_image_ep_info()
230 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
366 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); in bl31_plat_get_next_kernel64_ep_info()
412 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); in bl31_plat_get_next_kernel32_ep_info()
431 image_type = NON_SECURE; in bl31_prepare_kernel_entry()
|
| /external/arm-trusted-firmware/services/std_svc/spm_mm/ |
| D | spm_mm_main.c | 251 cm_el1_sysregs_context_save(NON_SECURE); in mm_communicate()
257 cm_el1_sysregs_context_restore(NON_SECURE); in mm_communicate()
258 cm_set_next_eret_context(NON_SECURE); in mm_communicate()
331 assert(handle == cm_get_context(NON_SECURE)); in spm_mm_smc_handler()
|
| /external/arm-trusted-firmware/bl31/ |
| D | bl31_context_mgmt.c | 22 assert(security_state <= NON_SECURE); in cm_get_context()
33 assert(security_state <= NON_SECURE); in cm_set_context()
|
| /external/arm-trusted-firmware/include/common/ |
| D | ep_info.h | 20 #define NON_SECURE EP_NON_SECURE macro
21 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/ |
| D | plat_sip_calls.c | 59 cm_set_elr_spsr_el3(NON_SECURE, x1, in plat_sip_handler()
63 cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); in plat_sip_handler()
|
| /external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
| D | bl31_zynqmp_setup.c | 35 if (type == NON_SECURE) { in bl31_plat_get_next_image_ep_info()
92 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
186 set_interrupt_rm_flag(flags, NON_SECURE); in bl31_plat_runtime_setup()
|
| /external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| D | context_mgmt.c | 143 if (security_state == NON_SECURE) in cm_setup_context()
170 (security_state == NON_SECURE))) { in cm_setup_context()
379 if (security_state == NON_SECURE) { in cm_prepare_el3_exit()
590 if ((security_state == NON_SECURE) || in cm_el2_sysregs_context_save()
612 if ((security_state == NON_SECURE) || in cm_el2_sysregs_context_restore()
|
| /external/arm-trusted-firmware/bl1/tbbr/ |
| D | tbbr_img_desc.c | 26 VERSION_1, entry_point_info_t, NON_SECURE | EXECUTABLE),
57 VERSION_1, entry_point_info_t, NON_SECURE),
|
| /external/arm-trusted-firmware/plat/qti/common/src/ |
| D | qti_bl31_setup.c | 129 assert(type == NON_SECURE); in bl31_plat_get_next_image_ep_info()
131 assert(bl33_image_ep_info.h.attr == NON_SECURE); in bl31_plat_get_next_image_ep_info()
|
| /external/arm-trusted-firmware/services/std_svc/sdei/ |
| D | sdei_intr_mgmt.c | 225 cm_el1_sysregs_context_restore(NON_SECURE); in restore_and_resume_ns_context()
226 cm_set_next_eret_context(NON_SECURE); in restore_and_resume_ns_context()
228 ns_ctx = cm_get_context(NON_SECURE); in restore_and_resume_ns_context()
265 cm_set_elr_spsr_el3(NON_SECURE, (uintptr_t) se->ep, in setup_ns_dispatch()
648 ctx = cm_get_context(NON_SECURE); in sdei_event_complete()
656 cm_set_elr_spsr_el3(NON_SECURE, pc, SPSR_64(client_el, in sdei_event_complete()
|
| /external/arm-trusted-firmware/plat/arm/common/aarch64/ |
| D | arm_bl2_mem_params_desc.c | 88 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
171 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
193 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
|
| D | execution_state_switch.c | 157 | NON_SECURE | EP_ST_DISABLE)); in arm_execution_state_switch()
165 cm_prepare_el3_exit(NON_SECURE); in arm_execution_state_switch()
|
| /external/arm-trusted-firmware/lib/psci/ |
| D | psci_setup.c | 82 NON_SECURE); in psci_init_pwr_domain_node()
311 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE); in psci_prepare_next_non_secure_ctx()
313 cm_prepare_el3_exit(NON_SECURE); in psci_prepare_next_non_secure_ctx()
|
| /external/arm-trusted-firmware/plat/arm/common/aarch32/ |
| D | arm_bl2_mem_params_desc.c | 60 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
70 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
|
| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | bl31_versal_setup.c | 37 if (type == NON_SECURE) { in bl31_plat_get_next_image_ep_info()
96 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
|
| /external/arm-trusted-firmware/plat/marvell/armada/common/ |
| D | marvell_bl31_setup.c | 49 next_image_info = (type == NON_SECURE) in bl31_plat_get_next_image_ep_info()
99 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in marvell_bl31_early_platform_setup()
|