1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CSS_DEF_H 8 #define CSS_DEF_H 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gic_common.h> 12 #include <drivers/arm/tzc400.h> 13 14 /************************************************************************* 15 * Definitions common to all ARM Compute SubSystems (CSS) 16 *************************************************************************/ 17 #define NSROM_BASE 0x1f000000 18 #define NSROM_SIZE 0x00001000 19 20 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 21 #define CSS_DEVICE_BASE 0x20000000 22 #define CSS_DEVICE_SIZE 0x0e000000 23 24 /* System Security Control Registers */ 25 #define SSC_REG_BASE 0x2a420000 26 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 27 28 /* System ID Registers Unit */ 29 #define SID_REG_BASE 0x2a4a0000 30 #define SID_SYSTEM_ID_OFFSET 0x40 31 #define SID_SYSTEM_CFG_OFFSET 0x70 32 #define SID_NODE_ID_OFFSET 0x60 33 #define SID_CHIP_ID_MASK 0xFF 34 #define SID_MULTI_CHIP_MODE_MASK 0x100 35 #define SID_MULTI_CHIP_MODE_SHIFT 8 36 37 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 38 #define CSS_NIC400_SLAVE_BOOTSECURE 8 39 40 /* Interrupt handling constants */ 41 #define CSS_IRQ_MHU 69 42 #define CSS_IRQ_GPU_SMMU_0 71 43 #define CSS_IRQ_TZC 80 44 #define CSS_IRQ_TZ_WDOG 86 45 #define CSS_IRQ_SEC_SYS_TIMER 91 46 47 /* MHU register offsets */ 48 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 49 50 /* 51 * Define a list of Group 1 Secure interrupt properties as per GICv3 52 * terminology. On a GICv2 system or mode, the interrupts will be treated as 53 * Group 0 interrupts. 54 */ 55 #define CSS_G1S_IRQ_PROPS(grp) \ 56 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ 57 GIC_INTR_CFG_LEVEL), \ 58 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 59 GIC_INTR_CFG_LEVEL), \ 60 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 61 GIC_INTR_CFG_LEVEL), \ 62 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 63 GIC_INTR_CFG_LEVEL), \ 64 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 65 GIC_INTR_CFG_LEVEL) 66 67 #if CSS_USE_SCMI_SDS_DRIVER 68 /* Memory region for shared data storage */ 69 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 70 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 71 /* 72 * The SCMI Channel is placed right after the SDS region 73 */ 74 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 75 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 76 77 /* Trusted mailbox base address common to all CSS */ 78 /* If SDS is present, then mailbox is at top of SRAM */ 79 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 80 81 /* Number of retries for SCP_RAM_READY flag */ 82 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 83 84 #else 85 /* 86 * SCP <=> AP boot configuration 87 * 88 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 89 * the start of the Trusted SRAM. 90 * 91 * Note that the value stored at this address is only valid at boot time, before 92 * the SCP_BL2 image is transferred to SCP. 93 */ 94 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 95 96 /* Trusted mailbox base address common to all CSS */ 97 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 98 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 99 100 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 101 102 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 103 CSS_DEVICE_BASE, \ 104 CSS_DEVICE_SIZE, \ 105 MT_DEVICE | MT_RW | MT_SECURE) 106 107 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 108 NSRAM_BASE, \ 109 NSRAM_SIZE, \ 110 MT_DEVICE | MT_RW | MT_NS) 111 112 #if defined(IMAGE_BL2U) 113 #define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ 114 SCP_BL2U_BASE, \ 115 SCP_BL2U_LIMIT \ 116 - SCP_BL2U_BASE,\ 117 MT_RW_DATA | MT_SECURE) 118 #endif 119 120 /* Platform ID address */ 121 #define SSC_VERSION_OFFSET 0x040 122 123 #define SSC_VERSION_CONFIG_SHIFT 28 124 #define SSC_VERSION_MAJOR_REV_SHIFT 24 125 #define SSC_VERSION_MINOR_REV_SHIFT 20 126 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 127 #define SSC_VERSION_PART_NUM_SHIFT 0x0 128 #define SSC_VERSION_CONFIG_MASK 0xf 129 #define SSC_VERSION_MAJOR_REV_MASK 0xf 130 #define SSC_VERSION_MINOR_REV_MASK 0xf 131 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 132 #define SSC_VERSION_PART_NUM_MASK 0xfff 133 134 #define SID_SYSTEM_ID_PART_NUM_MASK 0xfff 135 136 /* SSC debug configuration registers */ 137 #define SSC_DBGCFG_SET 0x14 138 #define SSC_DBGCFG_CLR 0x18 139 140 #define SPIDEN_INT_CLR_SHIFT 6 141 #define SPIDEN_SEL_SET_SHIFT 7 142 143 #ifndef __ASSEMBLER__ 144 145 /* SSC_VERSION related accessors */ 146 147 /* Returns the part number of the platform */ 148 #define GET_SSC_VERSION_PART_NUM(val) \ 149 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 150 SSC_VERSION_PART_NUM_MASK) 151 152 /* Returns the configuration number of the platform */ 153 #define GET_SSC_VERSION_CONFIG(val) \ 154 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 155 SSC_VERSION_CONFIG_MASK) 156 157 #endif /* __ASSEMBLER__ */ 158 159 /************************************************************************* 160 * Required platform porting definitions common to all 161 * ARM Compute SubSystems (CSS) 162 ************************************************************************/ 163 164 /* 165 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 166 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 167 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 168 * an SCP_BL2/SCP_BL2U image. 169 */ 170 #if CSS_LOAD_SCP_IMAGES 171 172 #if ARM_BL31_IN_DRAM 173 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 174 #endif 175 176 /* 177 * Load address of SCP_BL2 in CSS platform ports 178 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 179 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and 180 * BL31 is loaded over the top. 181 */ 182 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 183 #define SCP_BL2_LIMIT BL2_BASE 184 185 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 186 #define SCP_BL2U_LIMIT BL2_BASE 187 #endif /* CSS_LOAD_SCP_IMAGES */ 188 189 /* Load address of Non-Secure Image for CSS platform ports */ 190 #define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) 191 192 /* 193 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 194 * command 195 */ 196 #define CSS_CLUSTER_PWR_STATE_ON 0 197 #define CSS_CLUSTER_PWR_STATE_OFF 3 198 199 #define CSS_CPU_PWR_STATE_ON 1 200 #define CSS_CPU_PWR_STATE_OFF 0 201 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 202 203 #endif /* CSS_DEF_H */ 204