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Searched refs:NUM_META_FS_KEYS (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_constants.h46 #define NUM_META_FS_KEYS 12 macro
Dradv_private.h488 VkRenderPass render_pass[NUM_META_FS_KEYS];
489 VkPipeline color_pipelines[NUM_META_FS_KEYS];
511 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
514 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
517 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
520 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
538 VkPipeline pipelines[5][NUM_META_FS_KEYS];
545 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
591 VkPipeline pipeline[NUM_META_FS_KEYS];
592 VkRenderPass pass[NUM_META_FS_KEYS];
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Dradv_meta.h289 for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) { in radv_is_hw_resolve_pipeline()
Dradv_meta_blit2d.c691 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) { in radv_device_finish_meta_blit2d_state()
715 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) { in radv_device_finish_meta_blit2d_state()
1394 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) { in radv_device_init_meta_blit2d_state()
Dradv_meta_resolve.c263 for (uint32_t j = 0; j < NUM_META_FS_KEYS; j++) { in radv_device_finish_meta_resolve_state()
289 for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) { in radv_device_init_meta_resolve_state()
Dradv_meta_resolve_fs.c719 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) { in radv_device_init_meta_resolve_fragment_state()
772 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) { in radv_device_finish_meta_resolve_fragment_state()
Dradv_meta_blit.c759 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) { in radv_device_finish_meta_blit_state()
987 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) { in radv_device_init_meta_blit_color()
Dradv_meta_clear.c1360 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) { in radv_device_init_meta_clear_state()
Dradv_pipeline.c574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {