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Searched refs:NVC0C0_QMDV02_01_DEF (Results 1 – 1 of 1) sorted by relevance

/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dqmdc0c0.c26 #define NVC0C0_QMDV02_01_DEF(a...) NVQMD_DEF(NVC0C0, QMDV02_01, ##a) macro
42 NVC0C0_QMDV02_01_DEF(qmd, RUN_CTA_IN_ONE_SM_PARTITION, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
43 NVC0C0_QMDV02_01_DEF(qmd, IS_QUEUE, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
44 NVC0C0_QMDV02_01_DEF(qmd, ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
45 NVC0C0_QMDV02_01_DEF(qmd, SEMAPHORE_RELEASE_ENABLE0, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
46 NVC0C0_QMDV02_01_DEF(qmd, SEMAPHORE_RELEASE_ENABLE1, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
47 NVC0C0_QMDV02_01_DEF(qmd, REQUIRE_SCHEDULING_PCAS, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
48 NVC0C0_QMDV02_01_DEF(qmd, DEPENDENT_QMD_SCHEDULE_ENABLE, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
49 NVC0C0_QMDV02_01_DEF(qmd, DEPENDENT_QMD_TYPE, QUEUE, GRID); in NVC0C0QmdDump_V02_01()
50 NVC0C0_QMDV02_01_DEF(qmd, DEPENDENT_QMD_FIELD_COPY, FALSE, TRUE); in NVC0C0QmdDump_V02_01()
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