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Searched refs:NewOpc (Results 1 – 25 of 148) sorted by relevance

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/external/capstone/arch/X86/
DX86Disassembler.c204 unsigned NewOpc = 0; in translateImmediate() local
208 case X86_CMPPDrmi: NewOpc = X86_CMPPDrmi_alt; break; in translateImmediate()
209 case X86_CMPPDrri: NewOpc = X86_CMPPDrri_alt; break; in translateImmediate()
210 case X86_CMPPSrmi: NewOpc = X86_CMPPSrmi_alt; break; in translateImmediate()
211 case X86_CMPPSrri: NewOpc = X86_CMPPSrri_alt; break; in translateImmediate()
212 case X86_CMPSDrm: NewOpc = X86_CMPSDrm_alt; break; in translateImmediate()
213 case X86_CMPSDrr: NewOpc = X86_CMPSDrr_alt; break; in translateImmediate()
214 case X86_CMPSSrm: NewOpc = X86_CMPSSrm_alt; break; in translateImmediate()
215 case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; in translateImmediate()
216 case X86_VPCOMBri: NewOpc = X86_VPCOMBri_alt; break; in translateImmediate()
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp418 unsigned NewOpc; in translateImmediate() local
421 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; in translateImmediate()
422 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; in translateImmediate()
423 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; in translateImmediate()
424 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; in translateImmediate()
425 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; in translateImmediate()
426 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; in translateImmediate()
427 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; in translateImmediate()
428 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; in translateImmediate()
429 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; in translateImmediate()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86MCInstLower.cpp517 unsigned NewOpc; in Lower() local
520 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break; in Lower()
521 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break; in Lower()
522 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break; in Lower()
523 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break; in Lower()
525 OutMI.setOpcode(NewOpc); in Lower()
549 unsigned NewOpc; in Lower() local
552 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
553 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
554 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
[all …]
DX86EvexToVex.cpp149 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, in performCustomAdjustments() argument
151 (void)NewOpc; in performCustomAdjustments()
176 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
192 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments()
193 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments()
278 unsigned NewOpc = I->VexOpcode; in CompressEvexToVexImpl() local
283 if (!performCustomAdjustments(MI, NewOpc, ST)) in CompressEvexToVexImpl()
286 MI.setDesc(TII->get(NewOpc)); in CompressEvexToVexImpl()
DX86FixupLEAs.cpp598 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
604 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
610 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
636 unsigned NewOpc = in processInstrForSlow3OpLEA() local
638 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
642 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
643 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
671 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
693 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp502 unsigned NewOpc; in Lower() local
505 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
506 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
507 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
508 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
509 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
510 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
511 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
512 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
513 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
[all …]
DX86EvexToVex.cpp147 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { in performCustomAdjustments() argument
148 (void)NewOpc; in performCustomAdjustments()
155 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
171 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments()
172 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments()
259 unsigned NewOpc = I->VexOpcode; in CompressEvexToVexImpl() local
264 if (!performCustomAdjustments(MI, NewOpc)) in CompressEvexToVexImpl()
267 MI.setDesc(TII->get(NewOpc)); in CompressEvexToVexImpl()
DX86FixupLEAs.cpp577 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
583 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
589 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
615 unsigned NewOpc = in processInstrForSlow3OpLEA() local
617 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
621 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
622 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
648 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
649 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
[all …]
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp427 unsigned NewOpc; in Lower() local
430 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
431 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
432 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
433 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
434 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
435 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
436 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
437 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
438 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
[all …]
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp397 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
414 switch (NewOpc) { in genInstrWithNewOpc()
416 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
419 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
422 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
425 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
430 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
436 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
437 NewOpc == Mips::JIALC64) { in genInstrWithNewOpc()
439 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64) in genInstrWithNewOpc()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp594 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
616 switch (NewOpc) { in genInstrWithNewOpc()
618 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
621 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
624 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
627 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
630 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc()
633 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc()
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
644 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp224 unsigned OpNum, NewOpc; in rewrite() local
227 NewOpc = Hexagon::L2_loadri_io; in rewrite()
231 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
235 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
239 NewOpc = Hexagon::S2_storeri_io; in rewrite()
243 NewOpc = Hexagon::S2_storerd_io; in rewrite()
247 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
273 MI.setDesc(HII.get(NewOpc)); in rewrite()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp224 unsigned OpNum, NewOpc; in rewrite() local
227 NewOpc = Hexagon::L2_loadri_io; in rewrite()
231 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
235 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
239 NewOpc = Hexagon::S2_storeri_io; in rewrite()
243 NewOpc = Hexagon::S2_storerd_io; in rewrite()
247 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
273 MI.setDesc(HII.get(NewOpc)); in rewrite()
/external/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp210 unsigned OpNum, NewOpc; in rewrite() local
213 NewOpc = Hexagon::L2_loadri_io; in rewrite()
217 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
221 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
225 NewOpc = Hexagon::S2_storeri_io; in rewrite()
229 NewOpc = Hexagon::S2_storerd_io; in rewrite()
233 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
259 MI->setDesc(HII.get(NewOpc)); in rewrite()
/external/llvm-project/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp3605 unsigned NewOpc; in processInstruction() local
3608 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in processInstruction()
3609 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in processInstruction()
3610 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in processInstruction()
3611 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in processInstruction()
3612 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in processInstruction()
3613 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in processInstruction()
3614 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in processInstruction()
3615 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in processInstruction()
3616 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in processInstruction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1323 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1324 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1423 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1425 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1427 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1431 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1433 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1448 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1458 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1459 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
[all …]
DThumb2InstrInfo.cpp531 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local
533 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
564 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
574 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
586 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
591 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
651 if (NewOpc != Opcode) in rewriteT2FrameIndex()
652 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
696 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1773 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1780 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1787 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1794 if (!NewOpc) in optimizeThumb2Instructions()
1807 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1824 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1830 NewOpc = ARM::tB; in optimizeThumb2Branches()
1835 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1840 if (NewOpc) { in optimizeThumb2Branches()
1845 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
[all …]
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1261 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1361 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1363 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1365 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1369 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1371 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1386 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1395 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1396 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
[all …]
DThumb2InstrInfo.cpp504 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
505 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
538 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
548 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
560 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
565 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
592 if (NewOpc != Opcode) in rewriteT2FrameIndex()
593 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
626 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp595 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
617 switch (NewOpc) { in genInstrWithNewOpc()
619 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
622 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
625 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
628 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
631 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc()
634 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc()
639 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
645 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1325 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1326 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1475 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1477 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1479 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1483 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1485 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1500 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1510 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1511 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
[all …]
DARMConstantIslandPass.cpp1746 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1753 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1760 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1767 if (!NewOpc) in optimizeThumb2Instructions()
1780 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1797 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1803 NewOpc = ARM::tB; in optimizeThumb2Branches()
1808 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1813 if (NewOpc) { in optimizeThumb2Branches()
1818 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64PostSelectOptimize.cpp137 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local
141 if (InsideCmpRange && NewOpc) { in optimizeNZCVDefs()
145 II.setDesc(TII->get(NewOpc)); in optimizeNZCVDefs()
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp323 unsigned NewOpc; in convertCalleeSaveRestoreToSPPrePostIncDec() local
329 NewOpc = AArch64::STPXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
332 NewOpc = AArch64::STPDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
335 NewOpc = AArch64::STRXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
339 NewOpc = AArch64::STRDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
343 NewOpc = AArch64::LDPXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
346 NewOpc = AArch64::LDPDpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
349 NewOpc = AArch64::LDRXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
353 NewOpc = AArch64::LDRDpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
358 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)); in convertCalleeSaveRestoreToSPPrePostIncDec()

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