| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 934 TargetInstrInfo::RegSubRegPair NewSrc = in RewriteSource() local
944 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in RewriteSource()
958 MRI.clearKillFlags(NewSrc.Reg); in RewriteSource()
1213 TargetInstrInfo::RegSubRegPair NewSrc = CpyRewriter->getNewSource( in optimizeCoalescableCopy() local
1215 if (SrcReg == NewSrc.Reg || NewSrc.Reg == 0) in optimizeCoalescableCopy()
1219 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) { in optimizeCoalescableCopy()
1221 MRI->clearKillFlags(NewSrc.Reg); in optimizeCoalescableCopy()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 1196 RegSubRegPair NewSrc = getNewSource(MRI, TII, TrackPair, RewriteMap, in optimizeCoalescableCopy() local
1198 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0) in optimizeCoalescableCopy()
1202 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) { in optimizeCoalescableCopy()
1204 MRI->clearKillFlags(NewSrc.Reg); in optimizeCoalescableCopy()
1229 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource() local
1238 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1253 MRI->clearKillFlags(NewSrc.Reg); in rewriteSource()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 1201 RegSubRegPair NewSrc = getNewSource(MRI, TII, TrackPair, RewriteMap, in optimizeCoalescableCopy() local
1203 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0) in optimizeCoalescableCopy()
1207 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) { in optimizeCoalescableCopy()
1209 MRI->clearKillFlags(NewSrc.Reg); in optimizeCoalescableCopy()
1234 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource() local
1243 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1258 MRI->clearKillFlags(NewSrc.Reg); in rewriteSource()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInst.cpp | 457 Variable *NewSrc = Func->makeVariable(Dest->getType()); in lower() local
459 NewSrc->setName(Func, Dest->getName() + "_phi"); in lower()
460 if (auto *NewSrc64On32 = llvm::dyn_cast<Variable64On32>(NewSrc)) in lower()
462 this->Dest = NewSrc; in lower()
463 return InstAssign::create(Func, Dest, NewSrc); in lower()
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| D | IceInstX86BaseImpl.h | 2261 const Operand *NewSrc = Src; in emit() local
2267 NewSrc = SrcVar->asType(Func, DestTy, NewRegNum); in emit()
2269 NewSrc->emit(Func); in emit()
2809 const Variable *NewSrc = Src1Var->asType(Func, IceType_i32, NewRegNum); in emit() local
2810 NewSrc->emit(Func); in emit()
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| D | IceTargetLoweringARM32.cpp | 3546 Operand *NewSrc; in lowerAssign() local
3551 NewSrc = legalize(Src0, Legal_Reg | Legal_Flex, Dest->getRegNum()); in lowerAssign()
3556 NewSrc = legalize(Src0, Legal_Reg); in lowerAssign()
3560 NewSrc = legalize(NewSrc, Legal_Reg | Legal_Mem); in lowerAssign()
3562 _mov(Dest, NewSrc); in lowerAssign()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1061 SDValue NewSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
1063 if (NewSub || NewSrc) { in SimplifyDemandedBits()
1065 NewSrc = NewSrc ? NewSrc : Src; in SimplifyDemandedBits()
1066 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc, NewSub, in SimplifyDemandedBits()
1881 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
1883 return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); in SimplifyDemandedBits()
1934 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
1936 return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); in SimplifyDemandedBits()
1964 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
1966 return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); in SimplifyDemandedBits()
[all …]
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| D | LegalizeVectorTypes.cpp | 1892 SDValue NewSrc = in SplitVecRes_ExtendOp() local
1895 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl); in SplitVecRes_ExtendOp()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 231 unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
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| D | X86InstrInfo.cpp | 2566 unsigned Opc, bool AllowSP, unsigned &NewSrc, in classifyLEAReg() argument
2582 NewSrc = SrcReg; in classifyLEAReg()
2586 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && in classifyLEAReg()
2587 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) in classifyLEAReg()
2599 NewSrc = getX86SubSuperRegister(Src.getReg(), 64); in classifyLEAReg()
2601 MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI); in classifyLEAReg()
2621 NewSrc = MF.getRegInfo().createVirtualRegister(RC); in classifyLEAReg()
2623 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) in classifyLEAReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 224 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
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| D | X86InstrInfo.cpp | 704 unsigned Opc, bool AllowSP, Register &NewSrc, in classifyLEAReg() argument
720 NewSrc = SrcReg; in classifyLEAReg()
724 if (Register::isVirtualRegister(NewSrc) && in classifyLEAReg()
725 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) in classifyLEAReg()
737 NewSrc = getX86SubSuperRegister(Src.getReg(), 64); in classifyLEAReg()
743 NewSrc = MF.getRegInfo().createVirtualRegister(RC); in classifyLEAReg()
746 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) in classifyLEAReg()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 251 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
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| D | X86InstrInfo.cpp | 1189 unsigned Opc, bool AllowSP, Register &NewSrc, in classifyLEAReg() argument
1205 NewSrc = SrcReg; in classifyLEAReg()
1209 if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC)) in classifyLEAReg()
1221 NewSrc = getX86SubSuperRegister(Src.getReg(), 64); in classifyLEAReg()
1227 NewSrc = MF.getRegInfo().createVirtualRegister(RC); in classifyLEAReg()
1230 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) in classifyLEAReg()
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| D | X86ISelLowering.cpp | 11413 SDValue NewSrc = widenSubVector(Src, ZeroUppers, Subtarget, DAG, DL, 512); in getAVX512TruncNode() local
11414 return getAVX512TruncNode(DL, DstVT, NewSrc, Subtarget, DAG, ZeroUppers); in getAVX512TruncNode()
37761 if (SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( in SimplifyDemandedVectorEltsForTargetNode() local
37764 Op, TLO.DAG.getNode(Opc, SDLoc(Op), VT, NewSrc, Op.getOperand(1))); in SimplifyDemandedVectorEltsForTargetNode()
37968 if (SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( in SimplifyDemandedVectorEltsForTargetNode() local
37970 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, SDLoc(Op), VT, NewSrc)); in SimplifyDemandedVectorEltsForTargetNode()
38493 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBitsForTargetNode() local
38495 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, SDLoc(Op), VT, NewSrc)); in SimplifyDemandedBitsForTargetNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstructionCombining.cpp | 1885 auto *NewSrc = cast<GetElementPtrInst>( in visitGetElementPtrInst() local
1887 NewSrc->setIsInBounds(Src->isInBounds()); in visitGetElementPtrInst()
1888 auto *NewGEP = GetElementPtrInst::Create(GEPEltType, NewSrc, {SO1}); in visitGetElementPtrInst()
|
| /external/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstructionCombining.cpp | 2051 auto *NewSrc = cast<GetElementPtrInst>( in visitGetElementPtrInst() local
2053 NewSrc->setIsInBounds(Src->isInBounds()); in visitGetElementPtrInst()
2054 auto *NewGEP = GetElementPtrInst::Create(GEPEltType, NewSrc, {SO1}); in visitGetElementPtrInst()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 4288 TreePatternNodePtr NewSrc = P.SrcPattern->clone(); in ExpandHwModeBasedTypes() local
4290 if (!NewSrc->setDefaultMode(Mode) || !NewDst->setDefaultMode(Mode)) { in ExpandHwModeBasedTypes()
4297 PatternsToMatch.emplace_back(P.getSrcRecord(), Preds, std::move(NewSrc), in ExpandHwModeBasedTypes()
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 1934 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower() local
1937 MRI.setRegBank(NewSrc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in preISelLower()
1938 I.getOperand(1).setReg(NewSrc.getReg(0)); in preISelLower()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1306 SDValue NewSrc = in SplitVecRes_ExtendOp() local
1309 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl); in SplitVecRes_ExtendOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1754 SDValue NewSrc = in SplitVecRes_ExtendOp() local
1757 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl); in SplitVecRes_ExtendOp()
|
| D | TargetLowering.cpp | 1795 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
1797 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc)); in SimplifyDemandedBits()
|