| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 150 reg_(NoReg), in Operand()
157 reg_(NoReg), in Operand()
188 bool Operand::IsImmediate() const { return reg_.Is(NoReg); } in IsImmediate()
236 : base_(NoReg), in MemOperand()
237 regoffset_(NoReg), in MemOperand()
246 regoffset_(NoReg), in MemOperand()
295 regoffset_(NoReg), in MemOperand()
342 if (regoffset_.Is(NoReg)) { in IsEquivalentToPlainRegister()
355 return (addrmode_ == Offset) && regoffset_.Is(NoReg); in IsImmediateOffset()
360 return (addrmode_ == Offset) && !regoffset_.Is(NoReg); in IsRegisterOffset()
[all …]
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| D | registers-aarch64.h | 800 const Register NoReg;
839 const CPURegister& reg3 = NoReg,
840 const CPURegister& reg4 = NoReg,
841 const CPURegister& reg5 = NoReg,
842 const CPURegister& reg6 = NoReg,
843 const CPURegister& reg7 = NoReg,
844 const CPURegister& reg8 = NoReg);
864 const CPURegister& reg3 = NoReg,
865 const CPURegister& reg4 = NoReg,
866 const CPURegister& reg5 = NoReg,
[all …]
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| D | operands-aarch64.h | 479 regoffset_(NoReg), in base_()
498 regoffset_(NoReg), in base_()
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| D | macro-assembler-aarch64.cc | 552 VIXL_ASSERT((reg.Is(NoReg) || (type >= kBranchTypeFirstUsingReg)) && in B()
2174 PushHelper(2, size, src, src, NoReg, NoReg); in PushMultipleTimes()
2178 PushHelper(1, size, src, NoReg, NoReg, NoReg); in PushMultipleTimes()
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| D | macro-assembler-aarch64.h | 895 const CPURegister& src1 = NoReg,
896 const CPURegister& src2 = NoReg,
897 const CPURegister& src3 = NoReg);
899 const CPURegister& dst1 = NoReg,
900 const CPURegister& dst2 = NoReg,
901 const CPURegister& dst3 = NoReg);
1105 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1);
7154 const Register& reg2 = NoReg,
7155 const Register& reg3 = NoReg,
7156 const Register& reg4 = NoReg);
[all …]
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| D | assembler-aarch64.cc | 2026 VIXL_ASSERT(!addr.GetRegisterOffset().Is(NoReg) || in LoadStoreStructVerify()
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| /external/vixl/src/aarch32/ |
| D | operands-aarch32.h | 57 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
59 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
66 : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) { in Operand()
74 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(NoReg) { in Operand()
84 : imm_(0), rm_(rm), shift_(shift), amount_(amount), rs_(NoReg) { in Operand()
641 rm_(NoReg), in rn_()
658 rm_(NoReg), in rn_()
668 rm_(NoReg), in rn_()
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| D | instructions-aarch32.h | 418 const Register NoReg; variable
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| D | macro-assembler-aarch32.h | 853 CPURegister reg1 = NoReg,
854 CPURegister reg2 = NoReg,
855 CPURegister reg3 = NoReg,
856 CPURegister reg4 = NoReg);
11128 const Register& reg2 = NoReg,
11129 const Register& reg3 = NoReg,
11130 const Register& reg4 = NoReg) {
11146 const Register& reg2 = NoReg,
11147 const Register& reg3 = NoReg,
11148 const Register& reg4 = NoReg) {
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| /external/vixl/test/aarch64/ |
| D | test-abi.cc | 71 GenericOperand found(NoReg); in TEST()
72 GenericOperand expected(NoReg); in TEST()
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| D | test-api-aarch64.cc | 193 VIXL_CHECK(NoReg.Is(NoVReg)); in TEST()
194 VIXL_CHECK(NoVReg.Is(NoReg)); in TEST()
196 VIXL_CHECK(NoVReg.Is(NoReg)); in TEST()
197 VIXL_CHECK(NoReg.Is(NoVReg)); in TEST()
199 VIXL_CHECK(NoReg.Is(NoCPUReg)); in TEST()
200 VIXL_CHECK(NoCPUReg.Is(NoReg)); in TEST()
208 VIXL_CHECK(NoReg.IsNone()); in TEST()
382 VIXL_CHECK(!NoReg.IsValid()); in TEST()
453 VIXL_CHECK(!static_cast<CPURegister>(NoReg).IsValid()); in TEST()
1245 temps.Include(NoReg); in TEST()
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| D | test-utils-aarch64.cc | 550 Register first = NoReg; in Clobber()
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| /external/llvm-project/llvm/test/TableGen/ |
| D | nested-comment.td | 7 /*NoReg*/, baz
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| /external/llvm/test/TableGen/ |
| D | nested-comment.td | 7 /*NoReg*/, baz
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| /external/llvm-project/llvm/test/CodeGen/WebAssembly/ |
| D | fast-isel-noreg.ll | 4 ; Test that FastISel does not generate instructions with NoReg
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