| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 204 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
212 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
220 unsigned NumVecs, const uint16_t *DOpcodes,
226 void SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
232 void SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
268 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1689 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1690 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1808 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
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| D | ARMISelLowering.cpp | 9923 unsigned NumVecs = 0; in CombineBaseUpdate() local
9929 NumVecs = 1; break; in CombineBaseUpdate()
9931 NumVecs = 2; break; in CombineBaseUpdate()
9933 NumVecs = 3; break; in CombineBaseUpdate()
9935 NumVecs = 4; break; in CombineBaseUpdate()
9937 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
9939 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
9941 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
9943 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
9945 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 197 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
205 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
213 unsigned NumVecs, const uint16_t *DOpcodes,
266 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
273 unsigned NumVecs, const uint16_t *DOpcodes,
309 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1868 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1869 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1870 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2003 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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| D | ARMISelLowering.cpp | 13107 unsigned NumVecs = 0; in CombineBaseUpdate() local
13113 NumVecs = 1; break; in CombineBaseUpdate()
13115 NumVecs = 2; break; in CombineBaseUpdate()
13117 NumVecs = 3; break; in CombineBaseUpdate()
13119 NumVecs = 4; break; in CombineBaseUpdate()
13127 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
13129 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
13131 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
13133 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
13135 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 199 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
207 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
215 unsigned NumVecs, const uint16_t *DOpcodes,
272 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
293 unsigned NumVecs, const uint16_t *DOpcodes,
329 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1915 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1916 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1917 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2050 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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| D | ARMISelLowering.cpp | 14067 unsigned NumVecs = 0; in CombineBaseUpdate() local
14073 NumVecs = 1; break; in CombineBaseUpdate()
14075 NumVecs = 2; break; in CombineBaseUpdate()
14077 NumVecs = 3; break; in CombineBaseUpdate()
14079 NumVecs = 4; break; in CombineBaseUpdate()
14090 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
14092 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
14094 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
14096 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
14098 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 150 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable() argument
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| D | AArch64ISelLowering.cpp | 9229 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
9234 NumVecs = 2; break; in performNEONPostLDSTCombine()
9236 NumVecs = 3; break; in performNEONPostLDSTCombine()
9238 NumVecs = 4; break; in performNEONPostLDSTCombine()
9240 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
9242 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
9244 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
9246 NumVecs = 2; break; in performNEONPostLDSTCombine()
9248 NumVecs = 3; break; in performNEONPostLDSTCombine()
9250 NumVecs = 4; break; in performNEONPostLDSTCombine()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 241 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
248 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
250 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
252 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
253 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
254 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
268 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
269 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
270 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
271 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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| D | AArch64ISelLowering.cpp | 10396 template <unsigned NumVecs>
10406 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
10412 EC * NumVecs); in setInfoSVEStN()
14140 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
14145 NumVecs = 2; break; in performNEONPostLDSTCombine()
14147 NumVecs = 3; break; in performNEONPostLDSTCombine()
14149 NumVecs = 4; break; in performNEONPostLDSTCombine()
14151 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
14153 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
14155 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 206 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
213 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
215 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
217 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
218 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
220 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
221 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
222 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
223 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1164 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable() argument
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| D | AArch64ISelLowering.cpp | 11657 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
11662 NumVecs = 2; break; in performNEONPostLDSTCombine()
11664 NumVecs = 3; break; in performNEONPostLDSTCombine()
11666 NumVecs = 4; break; in performNEONPostLDSTCombine()
11668 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
11670 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
11672 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
11674 NumVecs = 2; break; in performNEONPostLDSTCombine()
11676 NumVecs = 3; break; in performNEONPostLDSTCombine()
11678 NumVecs = 4; break; in performNEONPostLDSTCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 669 unsigned NumVecs) { in createInterleaveMask() argument
672 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
727 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
728 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
734 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
736 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
743 if (NumVecs % 2 != 0) in concatenateVectors()
744 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
747 NumVecs = ResList.size(); in concatenateVectors()
748 } while (NumVecs > 1); in concatenateVectors()
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| /external/llvm-project/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 783 unsigned NumVecs) { in createInterleaveMask() argument
786 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
842 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
843 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
849 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
851 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
858 if (NumVecs % 2 != 0) in concatenateVectors()
859 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
862 NumVecs = ResList.size(); in concatenateVectors()
863 } while (NumVecs > 1); in concatenateVectors()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 337 unsigned NumVecs);
|
| /external/llvm-project/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 507 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10578 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10581 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
10585 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
10588 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10801 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
10802 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
10846 unsigned NumVecs = 2; in LowerVectorStore() local
10849 NumVecs = 4; in LowerVectorStore()
10851 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorStore()
10852 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
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| /external/llvm-project/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 14856 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
14859 NumVecs = 4; in EmitPPCBuiltinExpr()
14868 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 30142 unsigned NumVecs = VT.getSizeInBits() / 128; in combineToExtendVectorInReg() local
30148 for (unsigned i = 0, Offset = 0; i != NumVecs; ++i, Offset += NumSubElts) { in combineToExtendVectorInReg()
|