| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 246 case OP_ABS: in getLatency()
283 case OP_ABS: in getReadLatency()
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| D | nv50_ir_target_nvc0.cpp | 111 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
484 case OP_ABS: in isModSupported()
658 case OP_ABS: in getThroughput()
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| D | nv50_ir_lowering_nv50.cpp | 80 bld->mkOp1(OP_ABS, mul->sType, s[0], mul->getSrc(0)); in expandIntegerMUL()
81 bld->mkOp1(OP_ABS, mul->sType, s[1], mul->getSrc(1)); in expandIntegerMUL()
507 bld.mkOp1(OP_ABS, ty, a, div->getSrc(0)); in handleDIV()
508 bld.mkOp1(OP_ABS, ty, b, div->getSrc(1)); in handleDIV()
734 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), i->getSrc(c)); in handleTEX()
975 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), crd[c]); in handleTXD()
1054 bld.mkOp1(OP_ABS, TYPE_S32, i->getDef(0), i->getDef(0)); in handleSET()
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| D | nv50_ir_target_nv50.cpp | 91 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
462 case OP_ABS: in isModSupported()
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| D | nv50_ir_lowering_helper.cpp | 33 case OP_ABS: in visit()
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| D | nv50_ir_lowering_gm107.cpp | 156 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), crd[c]); in handleManualTXD()
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| D | nv50_ir_peephole.cpp | 539 case NV50_IR_MOD_ABS: return OP_ABS; in getOp()
880 case OP_ABS: res.data.f32 = fabsf(imm.reg.data.f32); break; in unary()
1305 Value *abs = bld.mkOp1v(OP_ABS, TYPE_S32, bld.getSSA(), i->getSrc(0)); in opnd()
1528 case OP_ABS: in opnd()
1737 (mi->op != OP_ABS && in visit()
1748 if ((i->op == OP_ABS) || i->src(s).mod.abs()) { in visit()
2093 if (!insn || insn->op != OP_ABS || insn->sType != TYPE_S32 || in handleCVT_NEG()
2365 case OP_ABS: in visit()
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| D | nv50_ir_emit_nv50.cpp | 1458 case OP_ABS: code[1] |= 1 << 20; break; in emitCVT()
1469 assert(i->op != OP_ABS || !i->src(0).mod.neg()); in emitCVT()
1938 case OP_ABS: in emitInstruction()
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| D | nv50_ir_emit_gm107.cpp | 824 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs()); in emitF2F()
866 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs()); in emitF2I()
908 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs()); in emitI2F()
941 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs()); in emitI2I()
3471 case OP_ABS: in emitInstruction()
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| D | nv50_ir_target_gv100.cpp | 208 case OP_ABS: in getOpInfo()
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| D | nv50_ir_emit_nvc0.cpp | 1097 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs(); in emitCVT()
1125 if (neg && i->op != OP_ABS) in emitCVT()
2783 case OP_ABS: in emitInstruction()
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| D | nv50_ir.h | 64 OP_ABS, enumerator
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| D | nv50_ir_lowering_nvc0.cpp | 794 case OP_ABS: in replaceCvt()
873 if (i->op == OP_SAT || i->op == OP_NEG || i->op == OP_ABS) in visit()
944 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), i->getSrc(c)); in handleTEX()
1251 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), crd[c]); in handleManualTXD()
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| D | nv50_ir_emit_gk110.cpp | 1071 case OP_ABS: abs = true; neg = false; break; in emitCVT()
2613 case OP_ABS: in emitInstruction()
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| D | nv50_ir.cpp | 38 case OP_ABS: bits = NV50_IR_MOD_ABS; break; in Modifier()
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| D | nv50_ir_from_tgsi.cpp | 1840 val = mkOp1v(OP_ABS, ty, getScratch(), val); in applySrcMod()
3201 mkOp1(OP_ABS, TYPE_F32, val0, src0); in handleInstruction()
3258 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0)); in handleInstruction()
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| D | nv50_ir_emit_gv100.cpp | 1686 case OP_ABS: in emitInstruction()
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| D | nv50_ir_from_nir.cpp | 384 return OP_ABS; in getOperation()
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