Searched refs:OP_EX2 (Results 1 – 15 of 15) sorted by relevance
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 128 case OP_EX2: in isBarrierRequired()
259 case OP_EX2: in getLatency()
287 case OP_EX2: in getReadLatency()
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| D | nv50_ir_target_nv50.cpp | 102 { OP_EX2, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0 },
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| D | nv50_ir_target_nvc0.cpp | 128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
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| D | nv50_ir_target_gv100.cpp | 267 case OP_EX2: in getOpInfo()
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| D | nv50_ir_emit_gv100.cpp | 557 case OP_EX2 : mufu = 2; break; in emitMUFU()
1767 case OP_EX2: in emitInstruction()
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| D | nv50_ir_lowering_nv50.cpp | 1259 i->op = OP_EX2; in handlePOW()
1411 case OP_EX2: in visit()
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| D | nv50_ir_emit_nv50.cpp | 1502 assert(subOp == 6 && i->op == OP_EX2); in emitSFnOp()
1969 case OP_EX2: in emitInstruction()
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| D | nv50_ir.h | 92 OP_EX2, enumerator
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| D | nv50_ir_from_tgsi.cpp | 3251 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0); in handleInstruction()
3253 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0); in handleInstruction()
3263 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1); in handleInstruction()
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| D | nv50_ir_emit_gm107.cpp | 1439 case OP_EX2: mufu = 2; break; in emitMUFU()
3609 case OP_EX2: in emitInstruction()
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| D | nv50_ir_lowering_nvc0.cpp | 3066 i->op = OP_EX2; in handlePOW()
3229 case OP_EX2: in visit()
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| D | nv50_ir_peephole.cpp | 885 case OP_EX2: res.data.f32 = exp2f(imm.reg.data.f32); break; in unary()
1539 case OP_EX2: in opnd()
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| D | nv50_ir_emit_gk110.cpp | 2637 case OP_EX2: in emitInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 2807 case OP_EX2: in emitInstruction()
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| D | nv50_ir_from_nir.cpp | 425 return OP_EX2; in getOperation()
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