| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_nvc0.cpp | 121 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
358 if ((i->op == OP_SHL || i->op == OP_SHR) && typeSizeof(i->sType) == 8 && in insnCanLoad()
656 case OP_SHR: in getThroughput()
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| D | nv50_ir_lowering_gm107.cpp | 321 bld.mkOp2(OP_SHR, TYPE_U32, suq->getDef(0), suq->getDef(0), in handleSUQ()
325 bld.mkOp2(OP_SHR, TYPE_U32, suq->getDef(d), suq->getDef(d), in handleSUQ()
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| D | nv50_ir_target_gm107.cpp | 235 case OP_SHR: in getLatency()
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| D | nv50_ir_lowering_gv100.cpp | 263 case OP_SHR: in visit()
353 bld.mkOp2(OP_SHR, TYPE_U32, i->getDef(0), mask, bit); in handleEXTBF()
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| D | nv50_ir_lowering_helper.cpp | 101 bld.mkOp2(OP_SHR, TYPE_S32, tmp, insn->getSrc(0), bld.loadImm(bld.getSSA(), 31)); in handleCVT()
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| D | nv50_ir_target_gv100.cpp | 371 case OP_SHR: return &opInfo_SHR; in getOpInfo()
495 if ((i->op == OP_SHL || i->op == OP_SHR) && in insnCanLoad()
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| D | nv50_ir_lowering_nvc0.cpp | 242 operation antiop = op == OP_SHR ? OP_SHL : OP_SHR; in handleShift()
243 if (op == OP_SHR) in handleShift()
261 if (op == OP_SHR) in handleShift()
275 if (lo->op == OP_SHR) in handleShift()
353 case OP_SHR: in visit()
1866 return bld.mkOp2v(OP_SHR, TYPE_U32, bld.getSSA(), tmp, bld.mkImm(2)); in loadMsAdjInfo32()
2038 src[2] = bld.mkOp2v(OP_SHR, TYPE_U32, bld.getSSA(), in processSurfaceCoordsNVE4()
2145 bld.mkOp2(OP_SHR, TYPE_U32, off, bf, bld.mkImm(8)); in processSurfaceCoordsNVE4()
2539 v = bld.mkOp2v(OP_SHR, TYPE_U32, bld.getSSA(), ind, bld.mkImm(11)); in processSurfaceCoordsGM107()
2544 bld.mkOp2(OP_SHR, TYPE_U32, v, v, bld.loadImm(NULL, 16)); in processSurfaceCoordsGM107()
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| D | nv50_ir_peephole.cpp | 676 case OP_SHR: in expr()
1101 i->op = OP_SHR; in opnd()
1221 i->op = OP_SHR; in opnd()
1245 bld.mkOp2(OP_SHR, TYPE_U32, tA, tB, bld.mkImm(r)); in opnd()
1251 bld.mkOp2(OP_SHR, TYPE_U32, i->getDef(0), tB, bld.mkImm(s)); in opnd()
1276 bld.mkOp2(OP_SHR, TYPE_S32, tB, tA, bld.mkImm(l - 1)); in opnd()
1431 src->op == OP_SHR && in opnd()
1472 case OP_SHR: in opnd()
2200 if (shift && shift->op == OP_SHR && in handleCVT_EXTBF()
2211 } else if (insn->op == OP_SHR && in handleCVT_EXTBF()
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| D | nv50_ir_target_nv50.cpp | 98 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
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| D | nv50_ir_lowering_nv50.cpp | 122 i[8] = bld->mkOp2(OP_SHR, fTy, r[0], t[1], bld->mkImm(halfSize * 8)); in expandIntegerMUL()
1197 bld.mkOp2(OP_SHR, TYPE_U32, def, def, bld.mkImm(16)); in handleRDSV()
1199 bld.mkOp2(OP_SHR, TYPE_U32, def, tid, bld.mkImm(26)); in handleRDSV()
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| D | nv50_ir_emit_nv50.cpp | 1584 code[1] = (i->op == OP_SHR) ? 0xe4000000 : 0xc4000000; in emitShift()
1585 if (i->op == OP_SHR && isSignedType(i->sType)) in emitShift()
1925 case OP_SHR: in emitInstruction()
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| D | nv50_ir_emit_gk110.cpp | 949 if (i->op == OP_SHR) { in emitShift()
964 if (i->op == OP_SHR) { in emitShift64()
2591 case OP_SHR: in emitInstruction()
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| D | nv50_ir.h | 72 OP_SHR, enumerator
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| D | nv50_ir_emit_nvc0.cpp | 970 if (i->op == OP_SHR) { in emitShift()
2764 case OP_SHR: in emitInstruction()
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| D | nv50_ir_from_nir.cpp | 483 return OP_SHR; in getOperation()
2670 mkOp2(OP_SHR, iType, val1, val0, loadImm(NULL, 31)); in visit()
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| D | nv50_ir_from_tgsi.cpp | 3870 mkOp2(OP_SHR, TYPE_S32, dst0[c + 1], dst0[c], loadImm(NULL, 31)); in handleInstruction()
4128 mkOp2(OP_SHR, TYPE_S32, dst0[c + 1], dst0[c], loadImm(0, 31)); in handleInstruction()
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| D | nv50_ir_emit_gm107.cpp | 3551 case OP_SHR: in emitInstruction()
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| /external/lua/src/ |
| D | lopcodes.h | 255 OP_SHR,/* A B C R[A] := R[B] >> R[C] */ enumerator
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| D | luac.c | 520 case OP_SHR: in PrintCode()
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| D | lcode.c | 1377 lua_assert(OP_ADD <= op && op <= OP_SHR); in codebinexpval()
1698 codebinexpval(fs, OP_SHR, e1, e2, line); in luaK_posfix()
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| D | lvm.c | 1452 vmcase(OP_SHR) { in luaV_execute()
1465 lua_assert(OP_ADD <= GET_OPCODE(pi) && GET_OPCODE(pi) <= OP_SHR); in luaV_execute()
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