| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 729 ORRS r7, r2, r1 // Must be wide - 3 distinct registers
730 ORRS r2, r2, r1 // Should choose narrow
731 ORRS r3, r1, r3 // Should choose narrow - commutative
732 ORRS.W r4, r4, r1 // Explicitly wide
733 ORRS.W r5, r1, r5
735 ORRS r7, r7, r1 // Should use narrow
736 ORRS r7, r1, r7 // Commutative
737 ORRS r8, r1, r8 // high registers so must use wide encoding
738 ORRS r8, r8, r1
739 ORRS r1, r8, r1
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 729 ORRS r7, r2, r1 // Must be wide - 3 distinct registers
730 ORRS r2, r2, r1 // Should choose narrow
731 ORRS r3, r1, r3 // Should choose narrow - commutative
732 ORRS.W r4, r4, r1 // Explicitly wide
733 ORRS.W r5, r1, r5
735 ORRS r7, r7, r1 // Should use narrow
736 ORRS r7, r1, r7 // Commutative
737 ORRS r8, r1, r8 // high registers so must use wide encoding
738 ORRS r8, r8, r1
739 ORRS r1, r8, r1
[all …]
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-const-a32.json | 43 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-rm-t32.json | 88 "Orrs", // ORRS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
89 // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 40 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 51 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 42 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 42 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 48 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 48 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-a32.json | 51 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x12.txt | 87 Instruction 82 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
126 Instruction 119 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
502 Instruction 486 S:0xC004309A 0xEA580009 1 ORRS r0,r8,r9 false
703 Instruction 683 S:0xC003FBC4 0xEA540605 1 ORRS r6,r4,r5 false
715 Instruction 695 S:0xC003FBE4 0xEA560807 2 ORRS r8,r6,r7 false
718 Instruction 698 S:0xC003FBEE 0xEA540C05 1 ORRS r12,r4,r5 false
821 Instruction 801 S:0xC00432FE 0xEA560E07 1 ORRS lr,r6,r7 false
1152 Instruction 1123 S:0xC0034614 0xEA520503 2 ORRS r5,r2,r3 false
1310 Instruction 1277 S:0xC0034D7C 0x430A 1 ORRS r2,r2,r1 false
1313 Instruction 1280 S:0xC0034D82 0x4303 2 ORRS r3,r3,r0 false
[all …]
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| D | etmv3_0x10.txt | 82 Instruction 73 S:0xC004F028 0x4332 1 ORRS r2,r2,r6 false fail
249 Instruction 227 S:0xC004F028 0x4332 1 ORRS r2,r2,r6 false fail
463 Instruction 431 S:0xC0025E6E 0x432B 1 ORRS r3,r3,r5 false
921 Instruction 860 S:0xC004F028 0x4332 1 ORRS r2,r2,r6 false fail
1478 Instruction 1356 S:0xC003B802 0xEA520903 1 ORRS r9,r2,r3 false
1673 Instruction 1551 S:0xC0042714 0xEA5A000B 1 ORRS r0,r10,r11 false
1884 Instruction 1758 S:0xC003FBC4 0xEA540605 1 ORRS r6,r4,r5 false
1896 Instruction 1770 S:0xC003FBE4 0xEA560807 2 ORRS r8,r6,r7 false
1899 Instruction 1773 S:0xC003FBEE 0xEA540C05 1 ORRS r12,r4,r5 false
2158 Instruction 2032 S:0xC00429C0 0xEA560E07 6 ORRS lr,r6,r7 false
[all …]
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| D | etmv3_0x11.txt | 26 Instruction 22 S:0xC0050938 0x430F 1 ORRS r7,r7,r1 false
240 Instruction 232 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
279 Instruction 269 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
848 Instruction 818 S:0xC003B884 0xEA540205 2 ORRS r2,r4,r5 false
1005 Instruction 975 S:0xC0043E5C 0xEA520103 1 ORRS r1,r2,r3 false
1069 Instruction 1039 S:0xC0043F28 0x4325 2 ORRS r5,r5,r4 false
1264 Instruction 1230 S:0xC003FBC4 0xEA540605 1 ORRS r6,r4,r5 false
1276 Instruction 1242 S:0xC003FBE4 0xEA560807 2 ORRS r8,r6,r7 false
1279 Instruction 1245 S:0xC003FBEE 0xEA540C05 1 ORRS r12,r4,r5 false
1407 Instruction 1373 S:0xC004414C 0xEA520003 2 ORRS r0,r2,r3 false
[all …]
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| D | ptmv1_0x13.txt | 406 Instruction 379 S:0xC00542EA 0x4330 0 ORRS r0,r0,r6 false
407 Instruction 380 S:0xC00542EC 0x4310 0 ORRS r0,r0,r2 false
1159 Instruction 1093 S:0xC004F028 0x4332 0 ORRS r2,r2,r6 false
1622 Instruction 1546 S:0xC003B884 0xEA540205 0 ORRS r2,r4,r5 false
1690 Instruction 1614 S:0xC0043E5C 0xEA520103 0 ORRS r1,r2,r3 false
1775 Instruction 1699 S:0xC0043F28 0x4325 0 ORRS r5,r5,r4 false
1982 Instruction 1901 S:0xC003FBC4 0xEA540605 0 ORRS r6,r4,r5 false
1994 Instruction 1913 S:0xC003FBE4 0xEA560807 0 ORRS r8,r6,r7 false
1997 Instruction 1916 S:0xC003FBEE 0xEA540C05 0 ORRS r12,r4,r5 false
2136 Instruction 2055 S:0xC004414C 0xEA520003 0 ORRS r0,r2,r3 false
[all …]
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| /external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/ds-5_trace_dump/ |
| D | a15_rs.txt | 136 S:0x80000932 4305 ORRS r5,r5,r0
472 S:0x80000932 4305 ORRS r5,r5,r0
824 S:0x80000932 4305 ORRS r5,r5,r0
1176 S:0x80000932 4305 ORRS r5,r5,r0
1528 S:0x80000932 4305 ORRS r5,r5,r0
1880 S:0x80000932 4305 ORRS r5,r5,r0
2232 S:0x80000932 4305 ORRS r5,r5,r0
2584 S:0x80000932 4305 ORRS r5,r5,r0
2936 S:0x80000932 4305 ORRS r5,r5,r0
3288 S:0x80000932 4305 ORRS r5,r5,r0
[all …]
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 152 #define ORRS 0x4300 macro
841 return push_inst16(compiler, ORRS | RD3(dst) | RN3(arg2)); in emit_op_imm()
|