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Searched refs:OUT_BATCH (Results 1 – 25 of 92) sorted by relevance

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/external/igt-gpu-tools/tools/null_state_gen/
Dintel_renderstate_gen7.c52 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | in gen7_emit_vertex_elements()
55 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen7_emit_vertex_elements()
60 OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | in gen7_emit_vertex_elements()
66 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen7_emit_vertex_elements()
69 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen7_emit_vertex_elements()
75 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen7_emit_vertex_elements()
78 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen7_emit_vertex_elements()
98 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2)); in gen7_emit_vertex_buffer()
99 OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | in gen7_emit_vertex_buffer()
106 OUT_BATCH(~0); in gen7_emit_vertex_buffer()
[all …]
Dintel_renderstate_gen9.c34 OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2)); in gen8_emit_wm()
35 OUT_BATCH(GEN8_WM_LEGACY_DIAMOND_LINE_RASTERIZATION); in gen8_emit_wm()
40 OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2)); in gen8_emit_ps()
41 OUT_BATCH(0); in gen8_emit_ps()
42 OUT_BATCH(0); /* kernel hi */ in gen8_emit_ps()
43 OUT_BATCH(GEN7_PS_SPF_MODE); in gen8_emit_ps()
44 OUT_BATCH(0); /* scratch space stuff */ in gen8_emit_ps()
45 OUT_BATCH(0); /* scratch hi */ in gen8_emit_ps()
46 OUT_BATCH(0); in gen8_emit_ps()
47 OUT_BATCH(0); in gen8_emit_ps()
[all …]
Dintel_renderstate_gen8.c35 OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2)); in gen8_emit_wm()
36 OUT_BATCH(GEN8_WM_LEGACY_DIAMOND_LINE_RASTERIZATION); in gen8_emit_wm()
41 OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2)); in gen8_emit_ps()
42 OUT_BATCH(0); in gen8_emit_ps()
43 OUT_BATCH(0); /* kernel hi */ in gen8_emit_ps()
44 OUT_BATCH(GEN7_PS_SPF_MODE); in gen8_emit_ps()
45 OUT_BATCH(0); /* scratch space stuff */ in gen8_emit_ps()
46 OUT_BATCH(0); /* scratch hi */ in gen8_emit_ps()
47 OUT_BATCH(0); in gen8_emit_ps()
48 OUT_BATCH(0); in gen8_emit_ps()
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Dintel_renderstate_gen6.c84 OUT_BATCH(GEN4_STATE_SIP | 0); in gen6_emit_sip()
85 OUT_BATCH(0); in gen6_emit_sip()
91 OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2)); in gen6_emit_urb()
92 OUT_BATCH((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT | in gen6_emit_urb()
94 OUT_BATCH(0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT | in gen6_emit_urb()
101 OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2)); in gen6_emit_state_base_address()
102 OUT_BATCH(0); /* general */ in gen6_emit_state_base_address()
109 OUT_BATCH(0); /* indirect */ in gen6_emit_state_base_address()
115 OUT_BATCH(0); in gen6_emit_state_base_address()
116 OUT_BATCH(BASE_ADDRESS_MODIFY); in gen6_emit_state_base_address()
[all …]
/external/igt-gpu-tools/lib/
Drendercopy_gen8.c329 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); in gen6_emit_vertex_elements()
334 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen6_emit_vertex_elements()
337 OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | in gen6_emit_vertex_elements()
348 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen6_emit_vertex_elements()
351 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen6_emit_vertex_elements()
360 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen6_emit_vertex_elements()
363 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen6_emit_vertex_elements()
377 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); in gen8_emit_vertex_buffer()
378 OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ in gen8_emit_vertex_buffer()
382 OUT_BATCH(3 * VERTEX_SIZE); in gen8_emit_vertex_buffer()
[all …]
Drendercopy_gen9.c372 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); in gen6_emit_vertex_elements()
377 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen6_emit_vertex_elements()
380 OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | in gen6_emit_vertex_elements()
391 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen6_emit_vertex_elements()
394 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen6_emit_vertex_elements()
403 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen6_emit_vertex_elements()
406 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen6_emit_vertex_elements()
420 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); in gen7_emit_vertex_buffer()
421 OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ in gen7_emit_vertex_buffer()
425 OUT_BATCH(3 * VERTEX_SIZE); in gen7_emit_vertex_buffer()
[all …]
Drendercopy_gen7.c118 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | in gen7_emit_vertex_elements()
121 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen7_emit_vertex_elements()
125 OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | in gen7_emit_vertex_elements()
131 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen7_emit_vertex_elements()
134 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen7_emit_vertex_elements()
140 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | in gen7_emit_vertex_elements()
143 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | in gen7_emit_vertex_elements()
183 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2)); in gen7_emit_vertex_buffer()
184 OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | in gen7_emit_vertex_buffer()
190 OUT_BATCH(~0); in gen7_emit_vertex_buffer()
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Drendercopy_gen6.c143 OUT_BATCH(GEN4_STATE_SIP | 0); in gen6_emit_sip()
144 OUT_BATCH(0); in gen6_emit_sip()
150 OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2)); in gen6_emit_urb()
151 OUT_BATCH((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT | in gen6_emit_urb()
153 OUT_BATCH(0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT | in gen6_emit_urb()
160 OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2)); in gen6_emit_state_base_address()
161 OUT_BATCH(0); /* general */ in gen6_emit_state_base_address()
168 OUT_BATCH(0); /* indirect */ in gen6_emit_state_base_address()
174 OUT_BATCH(0); in gen6_emit_state_base_address()
175 OUT_BATCH(BASE_ADDRESS_MODIFY); in gen6_emit_state_base_address()
[all …]
Drendercopy_i915.c32 OUT_BATCH(_3DSTATE_AA_CMD | in gen3_render_copyfunc()
36 OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | in gen3_render_copyfunc()
43 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in gen3_render_copyfunc()
44 OUT_BATCH(0); in gen3_render_copyfunc()
45 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in gen3_render_copyfunc()
46 OUT_BATCH(0); in gen3_render_copyfunc()
47 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in gen3_render_copyfunc()
48 OUT_BATCH(0); in gen3_render_copyfunc()
49 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | in gen3_render_copyfunc()
56 OUT_BATCH(_3DSTATE_RASTER_RULES_CMD | in gen3_render_copyfunc()
[all …]
Dgpu_cmds.c218 OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2)); in gen7_emit_state_base_address()
221 OUT_BATCH(0); in gen7_emit_state_base_address()
232 OUT_BATCH(0); in gen7_emit_state_base_address()
239 OUT_BATCH(0); in gen7_emit_state_base_address()
240 OUT_BATCH(0 | BASE_ADDRESS_MODIFY); in gen7_emit_state_base_address()
241 OUT_BATCH(0); in gen7_emit_state_base_address()
242 OUT_BATCH(0 | BASE_ADDRESS_MODIFY); in gen7_emit_state_base_address()
250 OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2)); in gen7_emit_vfe_state()
253 OUT_BATCH(0); in gen7_emit_vfe_state()
256 OUT_BATCH(threads << 16 | in gen7_emit_vfe_state()
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Drendercopy_i830.c80 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(i)); in gen2_emit_invariant()
81 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | MAP_UNIT(i) | in gen2_emit_invariant()
85 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); in gen2_emit_invariant()
86 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(i)); in gen2_emit_invariant()
89 OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD); in gen2_emit_invariant()
90 OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) | in gen2_emit_invariant()
95 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); in gen2_emit_invariant()
97 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM); in gen2_emit_invariant()
98 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE); in gen2_emit_invariant()
100 OUT_BATCH(_3DSTATE_W_STATE_CMD); in gen2_emit_invariant()
[all …]
Drendercopy_gen4.c204 OUT_BATCH(GEN4_STATE_SIP | (2 - 2)); in gen4_emit_sip()
205 OUT_BATCH(0); in gen4_emit_sip()
212 OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (8 - 2)); in gen4_emit_state_base_address()
219 OUT_BATCH(0); /* media */ in gen4_emit_state_base_address()
225 OUT_BATCH(BASE_ADDRESS_MODIFY); /* general */ in gen4_emit_state_base_address()
226 OUT_BATCH(0); /* media */ in gen4_emit_state_base_address()
227 OUT_BATCH(BASE_ADDRESS_MODIFY); /* instruction */ in gen4_emit_state_base_address()
229 OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (6 - 2)); in gen4_emit_state_base_address()
236 OUT_BATCH(0); /* media */ in gen4_emit_state_base_address()
239 OUT_BATCH(BASE_ADDRESS_MODIFY); /* general */ in gen4_emit_state_base_address()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH); in upload_pipelined_state_pointers()
67 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); in upload_pipelined_state_pointers()
72 OUT_BATCH(0); in upload_pipelined_state_pointers()
293 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); in brw_emit_depth_stencil_hiz()
294 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch_B - 1 : 0) | in brw_emit_depth_stencil_hiz()
303 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
306 OUT_BATCH(((width + tile_x - 1) << 6) | in brw_emit_depth_stencil_hiz()
308 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
311 OUT_BATCH(tile_x | (tile_y << 16)); in brw_emit_depth_stencil_hiz()
316 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
[all …]
Dhsw_sol.c105 OUT_BATCH(HSW_MI_MATH | (9 - 2)); in tally_prims_written()
107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
108 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
109 OUT_BATCH(MI_MATH_ALU0(SUB)); in tally_prims_written()
110 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU)); in tally_prims_written()
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
113 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
114 OUT_BATCH(MI_MATH_ALU0(ADD)); in tally_prims_written()
115 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU)); in tally_prims_written()
128 OUT_BATCH(HSW_MI_MATH | (5 - 2)); in tally_prims_written()
[all …]
Dgen8_multisample_state.c37 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2)); in gen8_emit_3dstate_sample_pattern()
40 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */ in gen8_emit_3dstate_sample_pattern()
41 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */ in gen8_emit_3dstate_sample_pattern()
42 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */ in gen8_emit_3dstate_sample_pattern()
43 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */ in gen8_emit_3dstate_sample_pattern()
46 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */ in gen8_emit_3dstate_sample_pattern()
47 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */ in gen8_emit_3dstate_sample_pattern()
50 OUT_BATCH(brw_multisample_positions_4x); in gen8_emit_3dstate_sample_pattern()
53 OUT_BATCH(brw_multisample_positions_1x_2x); in gen8_emit_3dstate_sample_pattern()
/external/igt-gpu-tools/tests/i915/
Dgem_unfence_active_buffers.c89 OUT_BATCH((3 << 24) | /* 32 bits */
92 OUT_BATCH(0 << 16 | 1024);
93 OUT_BATCH((2048) << 16 | (2048));
95 OUT_BATCH(0 << 16 | 0);
96 OUT_BATCH(2*1024*4);
102 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
103 OUT_BATCH(0);
104 OUT_BATCH(0);
122 OUT_BATCH((3 << 24) | /* 32 bits */
125 OUT_BATCH(0 << 16 | 0);
[all …]
Dgem_pipe_control_store_loop.c79 OUT_BATCH((3 << 24) | (0xf0 << 16) | 64); in store_pipe_control_loop()
80 OUT_BATCH(0); in store_pipe_control_loop()
81 OUT_BATCH(1 << 16 | 1); in store_pipe_control_loop()
91 OUT_BATCH(0xdeadbeef); in store_pipe_control_loop()
102 OUT_BATCH(GFX_OP_PIPE_CONTROL + 1); in store_pipe_control_loop()
103 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); in store_pipe_control_loop()
107 OUT_BATCH(val); /* write data */ in store_pipe_control_loop()
114 OUT_BATCH(GFX_OP_PIPE_CONTROL); in store_pipe_control_loop()
115 OUT_BATCH(PIPE_CONTROL_CS_STALL | in store_pipe_control_loop()
117 OUT_BATCH(0); /* address */ in store_pipe_control_loop()
[all …]
Dgem_write_read_ring_switch.c82 OUT_BATCH((3 << 24) | /* 32 bits */ in run_test()
85 OUT_BATCH(0); /* dst x1,y1 */ in run_test()
86 OUT_BATCH((1024 << 16) | 512); in run_test()
88 OUT_BATCH((0 << 16) | 512); /* src x1, y1 */ in run_test()
89 OUT_BATCH(4096); in run_test()
95 OUT_BATCH((3 << 24) | /* 32 bits */ in run_test()
98 OUT_BATCH(0); /* dst x1,y1 */ in run_test()
99 OUT_BATCH((1 << 16) | 1); in run_test()
101 OUT_BATCH(COLOR); in run_test()
109 OUT_BATCH(MI_NOOP); in run_test()
[all …]
Dgem_set_tiling_vs_blt.c89 OUT_BATCH((3 << 24) | /* 32 bits */ in do_test()
92 OUT_BATCH(0 << 16 | 1024); in do_test()
93 OUT_BATCH((2048) << 16 | (2048)); in do_test()
95 OUT_BATCH(0 << 16 | 0); in do_test()
96 OUT_BATCH(2*1024*4); in do_test()
102 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD); in do_test()
103 OUT_BATCH(0); in do_test()
104 OUT_BATCH(0); in do_test()
160 OUT_BATCH((3 << 24) | /* 32 bits */ in do_test()
163 OUT_BATCH(0 << 16 | 0); in do_test()
[all …]
/external/mesa3d/src/gallium/drivers/i915/
Di915_clear.c133 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); in i915_clear_emit()
135 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
136 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT); in i915_clear_emit()
138 OUT_BATCH(clear_color); in i915_clear_emit()
139 OUT_BATCH(clear_depth); in i915_clear_emit()
141 OUT_BATCH(clear_color8888); in i915_clear_emit()
143 OUT_BATCH(clear_stencil); in i915_clear_emit()
145 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); in i915_clear_emit()
153 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
154 OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) | in i915_clear_emit()
[all …]
Di915_state_emit.c68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE); in emit_flush()
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE); in emit_flush()
172 OUT_BATCH(fixup_imm); in emit_immediate_s5()
192 OUT_BATCH(imm); in emit_immediate_s6()
207 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | in emit_immediate()
215 OUT_BATCH(0); in emit_immediate()
225 OUT_BATCH(i915->current.immediate[i]); in emit_immediate()
242 OUT_BATCH(i915->current.dynamic[i]); in emit_dynamic()
274 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
275 OUT_BATCH(i915->current.cbuf_flags); in emit_static()
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Di915_blit.c78 OUT_BATCH(CMD); in i915_fill_blit()
79 OUT_BATCH(BR13); in i915_fill_blit()
80 OUT_BATCH((y << 16) | x); in i915_fill_blit()
81 OUT_BATCH(((y + h) << 16) | (x + w)); in i915_fill_blit()
83 OUT_BATCH(color); in i915_fill_blit()
150 OUT_BATCH(CMD); in i915_copy_blit()
151 OUT_BATCH(BR13); in i915_copy_blit()
152 OUT_BATCH((dst_y << 16) | dst_x); in i915_copy_blit()
153 OUT_BATCH((dst_y2 << 16) | dst_x2); in i915_copy_blit()
155 OUT_BATCH((src_y << 16) | src_x); in i915_copy_blit()
[all …]
Di915_prim_emit.c83 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
87 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
88 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
92 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
93 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
94 OUT_BATCH( fui(attrib[2]) ); in emit_hw_vertex()
98 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
99 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
100 OUT_BATCH( fui(attrib[2]) ); in emit_hw_vertex()
101 OUT_BATCH( fui(attrib[3]) ); in emit_hw_vertex()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Di830_vtbl.c304 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i830_emit_invarient_state()
305 OUT_BATCH(0); in i830_emit_invarient_state()
307 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i830_emit_invarient_state()
308 OUT_BATCH(0); in i830_emit_invarient_state()
310 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i830_emit_invarient_state()
311 OUT_BATCH(0); in i830_emit_invarient_state()
313 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); in i830_emit_invarient_state()
314 OUT_BATCH(FOGFUNC_ENABLE | in i830_emit_invarient_state()
316 OUT_BATCH(0); in i830_emit_invarient_state()
317 OUT_BATCH(0); in i830_emit_invarient_state()
[all …]
Di915_vtbl.c180 OUT_BATCH(_3DSTATE_AA_CMD | in i915_emit_invarient_state()
185 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i915_emit_invarient_state()
186 OUT_BATCH(0); in i915_emit_invarient_state()
188 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i915_emit_invarient_state()
189 OUT_BATCH(0); in i915_emit_invarient_state()
191 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i915_emit_invarient_state()
192 OUT_BATCH(0); in i915_emit_invarient_state()
195 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | in i915_emit_invarient_state()
202 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); in i915_emit_invarient_state()
203 OUT_BATCH(0); in i915_emit_invarient_state()
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