/external/exoplayer/tree/testdata/src/test/assets/ts/ |
D | sample_h264_dts_audio.ts | 36 l+ �S ��^/���SҝN|��9�2�oKH!�ؒ�H�v��n�.E�V3��0��P��CH��<e)�*�SK~���Z�D����2|i?�`OVF�$eה-i#�+�…
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D | sample_h264_mpeg_audio.ts | 36 l+ �S ��^/���SҝN|��9�2�oKH!�ؒ�H�v��n�.E�V3��0��P��CH��<e)�*�SK~���Z�D����2|i?�`OVF�$eה-i#�+�…
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 2324 SDValue OVF = Lo.getValue(1); in ExpandIntRes_ADDSUB() local 2328 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF); in ExpandIntRes_ADDSUB() 2331 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB() 2332 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB() 2335 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB() 2336 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.td | 129 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | R600ISelLowering.cpp | 873 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO() local 875 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO() 880 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | R600ISelLowering.cpp | 878 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO() local 880 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO() 885 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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/external/llvm/lib/Target/AMDGPU/ |
D | R600ISelLowering.cpp | 1047 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO() local 1049 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO() 1054 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 2581 SDValue OVF = Lo.getValue(1); in ExpandIntRes_ADDSUB() local 2585 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF); in ExpandIntRes_ADDSUB() 2588 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB() 2589 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB() 2592 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB() 2593 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.td | 122 // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc-
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 1777 SDValue OVF = Lo.getValue(1); in ExpandIntRes_ADDSUB() local 1781 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF); in ExpandIntRes_ADDSUB() 1784 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB() 1787 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.td | 136 // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc-
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/external/libaom/libaom/av1/encoder/ |
D | encoder.c | 1758 #define HIGHBD_OBFP(BT, OSDF, OVF, OSVF) \ argument 1760 cpi->fn_ptr[BT].ovf = OVF; \ 3380 #define OBFP(BT, OSDF, OVF, OSVF) \ in av1_create_compressor() argument 3382 cpi->fn_ptr[BT].ovf = OVF; \ in av1_create_compressor()
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/external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
D | 2013-1_UNLOCODE_CodeListPart2.csv | 3794 "+","GB","OVF","Ovenden","Ovenden","DNC","--3-----","RL","1301",,"5344N 00153W",
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D | 2013-1_UNLOCODE_CodeListPart3.csv | 11938 ,"US","OVF","Camptonville","Camptonville","CA","--3-----","RL","0901",,"3927N 12102W",
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D | 2013-1_UNLOCODE_CodeListPart1.csv | 29978 ,"ES","OVF","Oliva de la Frontera","Oliva de la Frontera",,"--3-----","RL","0212",,"3816N 00655W",
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