| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 66 unsigned Offset1,
131 unsigned Offset1, in offsetsCanBeCombined() argument
135 if (Offset0 == Offset1) in offsetsCanBeCombined()
139 if ((Offset0 % Size != 0) || (Offset1 % Size != 0)) in offsetsCanBeCombined()
143 unsigned EltOffset1 = Offset1 / Size; in offsetsCanBeCombined()
182 unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm() & 0xffff; in findMatchingDSInst() local
185 if (offsetsCanBeCombined(Offset0, Offset1, EltSize)) in findMatchingDSInst()
207 unsigned Offset1 in mergeRead2Pair() local
211 unsigned NewOffset1 = Offset1 / EltSize; in mergeRead2Pair()
303 unsigned Offset1 in mergeWrite2Pair() local
[all …]
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| D | AMDGPUInstrInfo.cpp | 51 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
53 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
59 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 50 int64_t Offset1, int64_t Offset2,
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| D | AMDGPUISelDAGToDAG.cpp | 91 SDValue &Offset1) const;
720 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
733 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
759 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
776 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
784 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
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| D | SIInstrInfo.cpp | 95 int64_t &Offset1) const { in areLoadsFromSameBasePtr()
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); in areLoadsFromSameBasePtr()
152 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr()
186 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr()
232 uint8_t Offset1 = Offset1Imm->getImm(); in getMemOpBaseRegImmOfs() local
234 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { in getMemOpBaseRegImmOfs()
1344 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
1347 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1356 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { in checkInstOffsetsDoNotOverlap()
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| /external/llvm-project/llvm/unittests/CodeGen/ |
| D | SelectionDAGAddressAnalysisTest.cpp | 135 TypeSize Offset1 = SubVecVT.getStoreSize(); in TEST_F() local
137 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F()
141 PtrInfo.getWithOffset(Offset1)); in TEST_F()
169 TypeSize Offset1 = SubVecVT.getStoreSize(); in TEST_F() local
171 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F()
175 PtrInfo.getWithOffset(Offset1)); in TEST_F()
239 TypeSize Offset1 = SubFixedVecVT2xi8.getStoreSize(); in TEST_F() local
241 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F()
245 PtrInfo.getWithOffset(Offset1)); in TEST_F()
282 TypeSize Offset1 = SubFixedVecVT2xi8.getStoreSize(); in TEST_F() local
[all …]
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| /external/llvm/lib/Fuzzer/test/ |
| D | CustomCrossOverTest.cpp | 43 size_t Offset1 = 0; in LLVMFuzzerCustomCrossOver() local
44 size_t Len1 = R() % (Size1 - Offset1); in LLVMFuzzerCustomCrossOver()
52 memcpy(Out, Data1 + Offset1, Len1); in LLVMFuzzerCustomCrossOver()
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelDAGToDAG.cpp | 429 int64_t Offset1 = Const->getSExtValue(); in doPeepholeLoadStoreADDI() local
430 int64_t CombinedOffset = Offset1 + Offset2; in doPeepholeLoadStoreADDI()
444 int64_t Offset1 = GA->getOffset(); in doPeepholeLoadStoreADDI() local
445 int64_t CombinedOffset = Offset1 + Offset2; in doPeepholeLoadStoreADDI()
454 int64_t Offset1 = CP->getOffset(); in doPeepholeLoadStoreADDI() local
455 int64_t CombinedOffset = Offset1 + Offset2; in doPeepholeLoadStoreADDI()
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| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | ConstraintElimination.cpp | 100 int64_t Offset1 = 0; in getConstraint() local
133 Offset1 = ADec[0].first; in getConstraint()
135 Offset1 *= -1; in getConstraint()
157 R[0] = Offset1 + Offset2 + (Pred == CmpInst::ICMP_ULT ? -1 : 0); in getConstraint()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 225 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
226 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
227 Offset1 == Offset2) in ClusterNeighboringLoads()
231 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
232 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
235 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 240 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
241 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
242 Offset1 == Offset2 || in ClusterNeighboringLoads()
248 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
249 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
252 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 243 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
244 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
245 Offset1 == Offset2 || in ClusterNeighboringLoads()
251 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
252 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
255 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 290 int64_t Offset1; in apply() local
292 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply()
298 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 207 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
211 SDValue &Offset1) const;
213 SDValue &Offset1) const;
215 SDValue &Offset1, unsigned Size) const;
1295 unsigned Offset1, in isDSOffset2Legal() argument
1297 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1299 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1314 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
1315 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1320 SDValue &Offset1) const { in SelectDS128Bit8ByteAligned()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 406 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
418 int64_t Offset1, int64_t Offset2,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 213 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
225 int64_t Offset1, int64_t Offset2,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 381 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
392 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| /external/llvm-project/llvm/tools/llvm-profgen/ |
| D | ProfiledBinary.cpp | 110 uint64_t Offset1 = virtualAddrToOffset(Address1); in inlineContextEqual() local
112 const FrameLocationStack &Context1 = getFrameLocationStack(Offset1); in inlineContextEqual()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 360 int64_t Offset1; in apply() local
362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply()
368 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 420 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
438 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 400 int64_t Offset1, Offset2; in ConsecutiveInstr() local
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 400 int64_t Offset1, Offset2; in ConsecutiveInstr() local
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
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| /external/llvm/test/CodeGen/SPARC/ |
| D | 64abi.ll | 505 ; HARD-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
507 ; HARD-DAG: ldx [%sp+[[Offset1]]], %o3
523 ; HARD: st %f0, [%fp+[[Offset1:[0-9]+]]]
528 ; HARD: ld [%fp+[[Offset1]]], %f1
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| /external/llvm-project/llvm/test/CodeGen/SPARC/ |
| D | 64abi.ll | 503 ; HARD-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
505 ; HARD-DAG: ldx [%sp+[[Offset1]]], %o3
521 ; HARD: st %f0, [%fp+[[Offset1:[0-9]+]]]
526 ; HARD: ld [%fp+[[Offset1]]], %f1
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 245 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
257 int64_t Offset1, int64_t Offset2,
|