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Searched refs:OffsetImm (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp784 const MCConstantExpr *OffsetImm; // Offset immediate value member
1042 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; in isThumbMemPC()
1044 Val = Memory.OffsetImm->getValue(); in isThumbMemPC()
1386 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffset()
1398 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffsetT2()
1410 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffsetT2NoSp()
1422 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffsetT()
1432 if (!Memory.OffsetImm) return true; in isMemPCRelImm12()
1433 int64_t Val = Memory.OffsetImm->getValue(); in isMemPCRelImm12()
1517 if (!Memory.OffsetImm) return true; in isAddrMode2()
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/external/llvm-project/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp850 const MCConstantExpr *OffsetImm; // Offset immediate value member
1108 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; in isThumbMemPC()
1110 Val = Memory.OffsetImm->getValue(); in isThumbMemPC()
1452 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffset()
1464 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffsetT2()
1476 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffsetT2NoSp()
1488 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffsetT()
1498 if (!Memory.OffsetImm) return true; in isMemPCRelImm12()
1499 int64_t Val = Memory.OffsetImm->getValue(); in isMemPCRelImm12()
1583 if (!Memory.OffsetImm) return true; in isAddrMode2()
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/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp513 const MCConstantExpr *OffsetImm; // Offset immediate value member
740 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; in isThumbMemPC()
742 Val = Memory.OffsetImm->getValue(); in isThumbMemPC()
1094 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffset()
1104 if (!Memory.OffsetImm) return true; in isMemPCRelImm12()
1105 int64_t Val = Memory.OffsetImm->getValue(); in isMemPCRelImm12()
1175 if (!Memory.OffsetImm) return true; in isAddrMode2()
1176 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode2()
1199 if (!Memory.OffsetImm) return true; in isAddrMode3()
1200 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode3()
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/external/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp667 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergeNarrowInsns() local
670 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge"); in mergeNarrowInsns()
671 OffsetImm /= 2; in mergeNarrowInsns()
688 .addImm(OffsetImm) in mergeNarrowInsns()
777 .addImm(OffsetImm) in mergeNarrowInsns()
856 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergePairedInsns() local
859 assert(!(OffsetImm % getMemScale(*RtMI)) && in mergePairedInsns()
861 OffsetImm /= getMemScale(*RtMI); in mergePairedInsns()
872 .addImm(OffsetImm) in mergePairedInsns()
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp541 unsigned OffsetImm = 0; in ReduceLoadStore() local
543 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
546 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) in ReduceLoadStore()
565 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfold-frame-offset-using-rr.mir5 # Imm instr: Reg = op OffsetImm, ToBeDeletedReg(killed)
9 # new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp570 unsigned OffsetImm = 0; in ReduceLoadStore() local
572 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
575 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) in ReduceLoadStore()
594 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
/external/llvm-project/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp580 unsigned OffsetImm = 0; in ReduceLoadStore() local
582 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
585 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) in ReduceLoadStore()
604 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp710 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergeNarrowZeroStores() local
713 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge"); in mergeNarrowZeroStores()
714 OffsetImm /= 2; in mergeNarrowZeroStores()
724 .addImm(OffsetImm) in mergeNarrowZeroStores()
909 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergePairedInsns() local
912 assert(!(OffsetImm % TII->getMemScale(*RtMI)) && in mergePairedInsns()
914 OffsetImm /= TII->getMemScale(*RtMI); in mergePairedInsns()
946 .addImm(OffsetImm) in mergePairedInsns()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp711 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergeNarrowZeroStores() local
714 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge"); in mergeNarrowZeroStores()
715 OffsetImm /= 2; in mergeNarrowZeroStores()
725 .addImm(OffsetImm) in mergeNarrowZeroStores()
909 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergePairedInsns() local
912 assert(!(OffsetImm % TII->getMemScale(*RtMI)) && in mergePairedInsns()
914 OffsetImm /= TII->getMemScale(*RtMI); in mergePairedInsns()
946 .addImm(OffsetImm) in mergePairedInsns()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringARM32.cpp5763 int32_t OffsetImm = 0; in formAddressingMode() local
5801 dumpAddressOpt(Func, BaseVar, OffsetImm, OffsetReg, OffsetRegShamt, in formAddressingMode()
5806 if (matchAssign(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5811 matchAssign(VMetadata, &OffsetReg, &OffsetImm, &Reason)) { in formAddressingMode()
5834 if (matchOffsetBase(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5850 Context.insert<InstAssign>(BaseVar, Ctx->getConstantInt32(OffsetImm)); in formAddressingMode()
5851 OffsetImm = 0; in formAddressingMode()
5852 } else if (OffsetImm != 0) { in formAddressingMode()
5856 const int32_t PositiveOffset = OffsetImm > 0 ? OffsetImm : -OffsetImm; in formAddressingMode()
5858 OffsetImm > 0 ? InstArithmetic::Add : InstArithmetic::Sub; in formAddressingMode()
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DIceTargetLoweringMIPS32.cpp5351 int32_t OffsetImm = 0; in formAddressingMode() local
5374 dumpAddressOpt(Func, BaseVar, OffsetImm, Reason); in formAddressingMode()
5378 if (matchAssign(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5382 if (matchOffsetBase(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5392 Context.insert<InstAssign>(BaseVar, Ctx->getConstantInt32(OffsetImm)); in formAddressingMode()
5393 OffsetImm = 0; in formAddressingMode()
5394 } else if (OffsetImm != 0) { in formAddressingMode()
5397 const int32_t PositiveOffset = OffsetImm > 0 ? OffsetImm : -OffsetImm; in formAddressingMode()
5399 OffsetImm > 0 ? InstArithmetic::Add : InstArithmetic::Sub; in formAddressingMode()
5401 if (!OperandMIPS32Mem::canHoldOffset(Ty, ZeroExt, OffsetImm)) { in formAddressingMode()
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/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp211 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
213 if (OffsetImm) { in getMemOpBaseRegImmOfs()
219 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
269 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
272 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
277 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
279 if (!OffsetImm) in getMemOpBaseRegImmOfs()
285 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h432 int64_t OffsetImm) const;
DPPCInstrInfo.cpp2546 int64_t OffsetImm = 0; in foldFrameOffset() local
2551 if (!isImmInstrEligibleForFolding(MI, ToBeDeletedReg, XFormOpcode, OffsetImm, in foldFrameOffset()
2574 if (isValidToBeChangedReg(ADDMI, 1, ADDIMI, OffsetAddi, OffsetImm)) in foldFrameOffset()
2576 else if (isValidToBeChangedReg(ADDMI, 2, ADDIMI, OffsetAddi, OffsetImm)) in foldFrameOffset()
2606 ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm); in foldFrameOffset()
2649 int64_t &OffsetImm, in isImmInstrEligibleForFolding() argument
2684 OffsetImm = ImmOperand.getImm(); in isImmInstrEligibleForFolding()
2692 int64_t OffsetImm) const { in isValidToBeChangedReg()
2726 if (isInt<16>(OffsetAddi + OffsetImm)) in isValidToBeChangedReg()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp2995 int64_t OffsetImm = 0; in foldFrameOffset() local
3000 if (!isImmInstrEligibleForFolding(MI, ToBeDeletedReg, XFormOpcode, OffsetImm, in foldFrameOffset()
3023 if (isValidToBeChangedReg(ADDMI, 1, ADDIMI, OffsetAddi, OffsetImm)) in foldFrameOffset()
3025 else if (isValidToBeChangedReg(ADDMI, 2, ADDIMI, OffsetAddi, OffsetImm)) in foldFrameOffset()
3062 ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm); in foldFrameOffset()
3109 int64_t &OffsetImm, in isImmInstrEligibleForFolding() argument
3144 OffsetImm = ImmOperand.getImm(); in isImmInstrEligibleForFolding()
3152 int64_t OffsetImm) const { in isValidToBeChangedReg()
3186 if (isInt<16>(OffsetAddi + OffsetImm)) in isValidToBeChangedReg()
DPPCInstrInfo.h598 int64_t OffsetImm) const;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp271 const MachineOperand *OffsetImm = in getMemOperandWithOffset() local
273 if (OffsetImm) { in getMemOperandWithOffset()
281 Offset = OffsetImm->getImm(); in getMemOperandWithOffset()
340 const MachineOperand *OffsetImm = in getMemOperandWithOffset() local
343 Offset = OffsetImm->getImm(); in getMemOperandWithOffset()
351 const MachineOperand *OffsetImm = in getMemOperandWithOffset() local
354 Offset = OffsetImm->getImm(); in getMemOperandWithOffset()
365 const MachineOperand *OffsetImm = in getMemOperandWithOffset() local
367 if (!OffsetImm) in getMemOperandWithOffset()
372 Offset = OffsetImm->getImm(); in getMemOperandWithOffset()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp361 const MachineOperand *OffsetImm = in getMemOperandsWithOffsetWidth() local
365 Offset = OffsetImm->getImm(); in getMemOperandsWithOffsetWidth()
376 const MachineOperand *OffsetImm = in getMemOperandsWithOffsetWidth() local
378 Offset = OffsetImm->getImm(); in getMemOperandsWithOffsetWidth()