Searched refs:Op0VT (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2720 EVT Op0VT = N0.getOperand(0).getValueType(); in SimplifyBinOpWithSameOpcodeHands() local
2726 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || in SimplifyBinOpWithSameOpcodeHands()
2728 (!TLI.isZExtFree(VT, Op0VT) || in SimplifyBinOpWithSameOpcodeHands()
2729 !TLI.isTruncateFree(Op0VT, VT)) && in SimplifyBinOpWithSameOpcodeHands()
2730 TLI.isTypeLegal(Op0VT))) && in SimplifyBinOpWithSameOpcodeHands()
2732 Op0VT == N1.getOperand(0).getValueType() && in SimplifyBinOpWithSameOpcodeHands()
2733 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { in SimplifyBinOpWithSameOpcodeHands()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 11486 EVT Op0VT = Op0.getOperand(0).getValueType(); in performVecReduceAddCombine() local
11487 if (Op0VT != MVT::v16i8) in performVecReduceAddCombine()
11491 SDValue Ones = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 14604 MVT Op0VT = Op0.getValueType().getSimpleVT(); in EmitKTEST() local
14605 if (Op0VT.isVector() && Op0VT.getVectorElementType() == MVT::i1 && in EmitKTEST()
14606 hasKTEST(Op0VT)) in EmitKTEST()
14607 return DAG.getNode(X86ISD::KTEST, SDLoc(Op), Op0VT, Op0, Op0); in EmitKTEST()
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