| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 142 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
[all …]
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| /external/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 142 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
[all …]
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 145 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
197 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
203 if (Op2.isImm()) { in getRiMemoryOpValue()
204 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
207 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
[all …]
|
| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 195 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) in Decode2OpInstruction() argument
213 *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2); in Decode2OpInstruction()
219 unsigned *Op1, unsigned *Op2, unsigned *Op3) in Decode3OpInstruction() argument
230 *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2); in Decode3OpInstruction()
312 unsigned Op1, Op2; in Decode2RInstruction() local
313 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
318 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
326 unsigned Op1, Op2; in Decode2RImmInstruction() local
327 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RImmInstruction()
332 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
[all …]
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
346 unsigned Op1, Op2; in Decode2RInstruction() local
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
359 unsigned Op1, Op2; in Decode2RImmInstruction() local
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
[all …]
|
| /external/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
346 unsigned Op1, Op2; in Decode2RInstruction() local
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
359 unsigned Op1, Op2; in Decode2RImmInstruction() local
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
[all …]
|
| /external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/ |
| D | NaClBitCodes.h | 238 const NaClBitCodeAbbrevOp &Op2) {
239 return Op1.Compare(Op2) < 0;
243 const NaClBitCodeAbbrevOp &Op2) {
244 return Op1.Compare(Op2) <= 0;
248 const NaClBitCodeAbbrevOp &Op2) {
249 return Op1.Compare(Op2) == 0;
253 const NaClBitCodeAbbrevOp &Op2) {
254 return Op1.Compare(Op2) != 0;
258 const NaClBitCodeAbbrevOp &Op2) {
259 return Op1.Compare(Op2) >= 0;
[all …]
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
99 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
111 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
114 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
295 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
302 if (Op2.isImm()) { in isSuitableAluInstr()
315 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
316 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
317 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
319 } else if (Op2.isReg()) { in isSuitableAluInstr()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
294 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
301 if (Op2.isImm()) { in isSuitableAluInstr()
314 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
315 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
316 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
294 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
301 if (Op2.isImm()) { in isSuitableAluInstr()
314 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
315 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
316 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 283 const MachineMemOperand &Op2, in alias() argument
285 if (!Op1.getValue() || !Op2.getValue()) in alias()
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
290 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
295 MemoryLocation(Op2.getValue(), Overlapb, in alias()
296 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
309 if (alias(*Op1, *Op2, UseTBAA)) in alias()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 283 const MachineMemOperand &Op2, in alias() argument
285 if (!Op1.getValue() || !Op2.getValue()) in alias()
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
290 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
295 MemoryLocation(Op2.getValue(), Overlapb, in alias()
296 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
309 if (alias(*Op1, *Op2, UseTBAA)) in alias()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
141 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
153 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
156 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
|
| /external/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
141 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
153 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
156 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIPreEmitPeephole.cpp | 96 MachineOperand &Op2 = A->getOperand(2); in optimizeVccBranch() local
97 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
103 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0)) in optimizeVccBranch()
108 if (Op2.isReg()) { in optimizeVccBranch()
109 SReg = Op2.getReg(); in optimizeVccBranch()
125 if (!ReadsSreg && Op2.isKill()) { in optimizeVccBranch()
129 } else if (Op2.isImm()) { in optimizeVccBranch()
130 MaskValue = Op2.getImm(); in optimizeVccBranch()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | SVEIntrinsicOpts.cpp | 145 IntrinsicInst *Op2 = dyn_cast<IntrinsicInst>(I->getArgOperand(1)); in optimizePTest() local
147 if (Op1 && Op2 && in optimizePTest()
149 Op2->getIntrinsicID() == Intrinsic::aarch64_sve_convert_to_svbool && in optimizePTest()
150 Op1->getArgOperand(0)->getType() == Op2->getArgOperand(0)->getType()) { in optimizePTest()
152 Value *Ops[] = {Op1->getArgOperand(0), Op2->getArgOperand(0)}; in optimizePTest()
163 if (Op1 != Op2 && Op2->use_empty()) in optimizePTest()
164 Op2->eraseFromParent(); in optimizePTest()
|
| /external/tensorflow/tensorflow/core/api_def/ |
| D | update_api_def_test.cc | 83 REGISTER_OP("Op2") in TEST()
100 REGISTER_OP("Op2") in TEST()
104 Summary for Op2. in TEST()
123 name: "Op2" in TEST()
127 summary: "Summary for Op2." in TEST()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
129 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
131 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
131 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySelectionDAGInfo.h | 26 SDValue Chain, SDValue Op1, SDValue Op2,
32 SDValue Chain, SDValue Op1, SDValue Op2,
37 SDValue Chain, SDValue Op1, SDValue Op2,
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySelectionDAGInfo.h | 26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
|
| /external/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| D | BPFAsmParser.cpp | 270 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
274 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck()
275 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck()
276 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck()
277 || Op2.getToken() == "le64") in PreMatchCheck()
|