/external/llvm-project/llvm/utils/TableGen/ |
D | CodeGenSchedule.h | 318 llvm::APInt OperandMask; // An operand mask. member 321 : ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {} in PredicateInfo() 325 OperandMask == Other.OperandMask && Predicate == Other.Predicate; 347 const llvm::APInt &OperandMask,
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D | CodeGenSchedule.cpp | 269 APInt OperandMask; in constructOperandMask() local 271 return OperandMask; in constructOperandMask() 275 OperandMask = OperandMask.zext(MaxIndex + 1); in constructOperandMask() 278 OperandMask.setBit(Index); in constructOperandMask() 281 return OperandMask; in constructOperandMask() 341 APInt OperandMask = constructOperandMask(OpIndices); in processSTIPredicate() local 359 OI.addPredicateForProcModel(ProcMask, OperandMask, Pred); in processSTIPredicate() 426 const llvm::APInt &OperandMask, in addPredicateForProcModel() argument 429 Predicates, [&OperandMask, &Predicate](const PredicateInfo &P) { in addPredicateForProcModel() 430 return P.Predicate == Predicate && P.OperandMask == OperandMask; in addPredicateForProcModel() [all …]
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D | PredicateExpander.cpp | 473 if (PI.OperandMask.isNullValue()) in expandOpcodeGroup() 476 OS << "Mask = " << PI.OperandMask << ";\n"; in expandOpcodeGroup()
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D | AsmMatcherEmitter.cpp | 694 unsigned OperandMask; member 701 X.OperandMask = opMask; in create() 1455 unsigned &OperandMask = OpClassMask[Op.Class]; in buildOperandMatchInfo() local 1456 OperandMask |= (1 << i); in buildOperandMatchInfo() 2837 MaxMask |= OMI.OperandMask; in emitCustomOperandParsing() 2887 OS << OMI.OperandMask; in emitCustomOperandParsing() 2891 if (OMI.OperandMask & (1 << i)) { in emitCustomOperandParsing()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | GCNRegBankReassign.cpp | 75 class OperandMask { class in __anon8074828c0111::GCNRegBankReassign 77 OperandMask(unsigned r, unsigned s, unsigned m) in OperandMask() function in __anon8074828c0111::GCNRegBankReassign::OperandMask 158 SmallVector<OperandMask, 8> OperandMasks; 395 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask)); in analyzeInst()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | GCNRegBankReassign.cpp | 76 class OperandMask { class in __anondebd7f180111::GCNRegBankReassign 78 OperandMask(unsigned r, unsigned s, unsigned m) in OperandMask() function in __anondebd7f180111::GCNRegBankReassign::OperandMask 177 SmallVector<OperandMask, 8> OperandMasks; 448 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask)); in analyzeInst()
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/external/llvm/utils/TableGen/ |
D | AsmMatcherEmitter.cpp | 679 unsigned OperandMask; member 686 X.OperandMask = opMask; in create() 1424 unsigned &OperandMask = OpClassMask[Op.Class]; in buildOperandMatchInfo() local 1425 OperandMask |= (1 << i); in buildOperandMatchInfo() 2643 MaxMask |= OMI.OperandMask; in emitCustomOperandParsing() 2704 OS << ", " << OMI.OperandMask; in emitCustomOperandParsing() 2708 if (OMI.OperandMask & (1 << i)) { in emitCustomOperandParsing()
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenAsmMatcher.inc | 8293 uint8_t OperandMask; 11732 if (!(it->OperandMask & (1 << NextOpNum)))
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 15348 uint8_t OperandMask; 16395 if (!(it->OperandMask & (1 << NextOpNum)))
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenAsmMatcher.inc | 27681 uint8_t OperandMask; 40960 if (!(it->OperandMask & (1 << NextOpNum)))
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