| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | fmf-propagation.ll | 17 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_contract1:'
40 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_contract2:'
63 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_reassoc1:'
86 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_reassoc2:'
109 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast1:'
132 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast2:'
156 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
160 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
185 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc2:'
189 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc2:'
[all …]
|
| D | add_cmp.ll | 12 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiUnsigned:entry'
25 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiSigned:entry'
38 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiUnsignedOverflow:entry'
51 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiSignedOverflow:entry'
|
| /external/libyuv/files/ |
| D | README.md | 7 * Optimized for SSSE3/AVX2 on x86/x64.
8 * Optimized for Neon on Arm.
9 * Optimized for MSA on Mips.
|
| /external/compiler-rt/make/ |
| D | lib_util.mk | 31 $(if $(and $(call streq,Optimized,$($(key).Implementation)),\
36 $(if $(and $(call streq,Optimized,$($(key).Implementation)),\
40 $(if $(and $(call streq,Optimized,$($(key).Implementation)),\
|
| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | combine_loads_from_build_pair.ll | 6 ; between "Initial selection DAG" and "Optimized lowered selection DAG".
18 ; CHECK-LABEL: Optimized lowered selection DAG:
|
| /external/llvm/include/llvm/CodeGen/ |
| D | TargetPassConfig.h | 303 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
371 FunctionPass *createRegAllocPass(bool Optimized);
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | fmf-propagation.ll | 17 ; CHECK: Optimized lowered selection DAG: %bb.0 'fmf_transfer:'
31 ; CHECK-LABEL: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:'
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetPassConfig.h | 363 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
446 virtual FunctionPass *createRegAllocPass(bool Optimized);
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetPassConfig.h | 379 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
457 virtual FunctionPass *createRegAllocPass(bool Optimized);
|
| /external/compiler-rt/lib/builtins/armv6m/ |
| D | Makefile.mk | 17 Implementation := Optimized
|
| /external/compiler-rt/lib/builtins/ppc/ |
| D | Makefile.mk | 17 Implementation := Optimized
|
| /external/compiler-rt/lib/builtins/i386/ |
| D | Makefile.mk | 17 Implementation := Optimized
|
| /external/compiler-rt/lib/builtins/arm64/ |
| D | Makefile.mk | 17 Implementation := Optimized
|
| /external/compiler-rt/lib/builtins/x86_64/ |
| D | Makefile.mk | 17 Implementation := Optimized
|
| /external/compiler-rt/lib/builtins/arm/ |
| D | Makefile.mk | 17 Implementation := Optimized
|
| /external/mesa3d/docs/ |
| D | perf.rst | 18 #. Optimized polygon rasterizers are employed when: rendering into back
23 #. Optimized line drawing is employed when: rendering into back buffer
|
| /external/compiler-rt/test/builtins/Unit/ppc/ |
| D | test | 2 if gcc -arch ppc -O0 $FILE ../../../Release/ppc/libcompiler_rt.Optimized.a -mlong-double-128
|
| /external/llvm-project/compiler-rt/test/builtins/Unit/ppc/ |
| D | test | 2 if gcc -arch ppc -O0 $FILE ../../../Release/ppc/libcompiler_rt.Optimized.a -mlong-double-128
|
| /external/arm-optimized-routines/ |
| D | METADATA | 2 description: "Optimized implementations of various library functions for ARM architecture processor…
|
| /external/libpng/ |
| D | README | 150 arm-neon => Optimized code for ARM-NEON platform
151 powerpc-vsx => Optimized code for POWERPC-VSX platform
157 mips-msa => Optimized code for MIPS-MSA platform
165 intel => Optimized code for INTEL-SSE2 platform
166 mips => Optimized code for MIPS platform
|
| /external/llvm/bindings/go/llvm/ |
| D | dibuilder.go | 118 Optimized bool member
138 boolToCInt(cu.Optimized),
191 Optimized bool member
212 boolToCInt(f.Optimized),
|
| /external/llvm/lib/CodeGen/ |
| D | TargetPassConfig.cpp | 752 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { in createTargetRegisterAllocator() argument
753 if (Optimized) in createTargetRegisterAllocator()
768 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { in createRegAllocPass() argument
778 return createTargetRegisterAllocator(Optimized); in createRegAllocPass()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsDerived.td | 12 // Optimized with intrinisics accumulates
|
| /external/llvm-project/llvm/docs/GlobalISel/ |
| D | Resources.rst | 11 * `Generating Optimized Code with GlobalISel by Volkan Keles, Daniel Sanders @LLVMDevMeeting 2019 <…
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | cmpb-dec-imm.ll | 5 ; The "Optimized Lowered Selection" converts the "ugt with #40" to
|