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Searched refs:Orders (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp702 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
719 Orders.push_back(std::make_pair(DVOrder, DbgMI)); in ProcessSDDbgValues()
733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSourceNode()
739 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
749 Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr)); in ProcessSourceNode()
753 Orders.push_back(std::make_pair(Order, &*std::prev(Emitter.getInsertPos()))); in ProcessSourceNode()
754 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
842 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); in EmitSchedule()
849 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, in EmitSchedule()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
749 Orders.push_back({DVOrder, DbgMI}); in ProcessSDDbgValues()
762 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders, in ProcessSourceNode() argument
768 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
778 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
783 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
831 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
911 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn); in EmitSchedule()
923 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen, in EmitSchedule()
940 llvm::stable_sort(Orders, less_first()); in EmitSchedule()
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DFastISel.cpp240 Orders[&I] = Order++; in initialize()
267 OrderMap.Orders.erase(&LocalMI); in sinkLocalValueMaterialization()
274 if (OrderMap.Orders.empty()) in sinkLocalValueMaterialization()
281 auto I = OrderMap.Orders.find(&UseInst); in sinkLocalValueMaterialization()
282 assert(I != OrderMap.Orders.end() && in sinkLocalValueMaterialization()
311 unsigned UseOrder = OrderMap.Orders[&DbgVal]; in sinkLocalValueMaterialization()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp737 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
753 Orders.push_back({DVOrder, DbgMI}); in ProcessSDDbgValues()
766 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders, in ProcessSourceNode() argument
772 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
782 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
787 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
835 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
920 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn); in EmitSchedule()
932 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen, in EmitSchedule()
949 llvm::stable_sort(Orders, less_first()); in EmitSchedule()
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DFastISel.cpp254 Orders[&I] = Order++; in initialize()
281 OrderMap.Orders.erase(&LocalMI); in sinkLocalValueMaterialization()
288 if (OrderMap.Orders.empty()) in sinkLocalValueMaterialization()
295 auto I = OrderMap.Orders.find(&UseInst); in sinkLocalValueMaterialization()
296 assert(I != OrderMap.Orders.end() && in sinkLocalValueMaterialization()
325 unsigned UseOrder = OrderMap.Orders[&DbgVal]; in sinkLocalValueMaterialization()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DInlineSpiller.cpp128 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1229 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders() argument
1288 Orders.push_back(MDT.getBase().getNode(Root)); in getVisitOrders()
1290 MachineDomTreeNode *Node = Orders[idx++]; in getVisitOrders()
1296 Orders.push_back(Child); in getVisitOrders()
1298 } while (idx != Orders.size()); in getVisitOrders()
1299 assert(Orders.size() == WorkSet.size() && in getVisitOrders()
1303 LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); in getVisitOrders()
1304 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); in getVisitOrders()
1305 for (; RIt != Orders.rend(); RIt++) in getVisitOrders()
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/external/llvm-project/llvm/lib/CodeGen/
DInlineSpiller.cpp129 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1259 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders() argument
1318 Orders.push_back(MDT.getBase().getNode(Root)); in getVisitOrders()
1320 MachineDomTreeNode *Node = Orders[idx++]; in getVisitOrders()
1323 Orders.push_back(Child); in getVisitOrders()
1325 } while (idx != Orders.size()); in getVisitOrders()
1326 assert(Orders.size() == WorkSet.size() && in getVisitOrders()
1330 LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); in getVisitOrders()
1331 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); in getVisitOrders()
1332 for (; RIt != Orders.rend(); RIt++) in getVisitOrders()
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/external/llvm/lib/CodeGen/
DInlineSpiller.cpp99 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1142 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders() argument
1201 Orders.push_back(MDT.DT->getNode(Root)); in getVisitOrders()
1203 MachineDomTreeNode *Node = Orders[idx++]; in getVisitOrders()
1209 Orders.push_back(Child); in getVisitOrders()
1211 } while (idx != Orders.size()); in getVisitOrders()
1212 assert(Orders.size() == WorkSet.size() && in getVisitOrders()
1216 DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); in getVisitOrders()
1217 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); in getVisitOrders()
1218 for (; RIt != Orders.rend(); RIt++) in getVisitOrders()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DConstantHoisting.cpp249 SmallVector<BasicBlock *, 16> Orders; in findBestInsertionSet() local
250 Orders.push_back(Entry); in findBestInsertionSet()
251 while (Idx != Orders.size()) { in findBestInsertionSet()
252 BasicBlock *Node = Orders[Idx++]; in findBestInsertionSet()
255 Orders.push_back(ChildDomNode->getBlock()); in findBestInsertionSet()
266 InsertPtsMap.reserve(Orders.size() + 1); in findBestInsertionSet()
267 for (auto RIt = Orders.rbegin(); RIt != Orders.rend(); RIt++) { in findBestInsertionSet()
/external/llvm-project/llvm/lib/Transforms/Scalar/
DConstantHoisting.cpp249 SmallVector<BasicBlock *, 16> Orders; in findBestInsertionSet() local
250 Orders.push_back(Entry); in findBestInsertionSet()
251 while (Idx != Orders.size()) { in findBestInsertionSet()
252 BasicBlock *Node = Orders[Idx++]; in findBestInsertionSet()
255 Orders.push_back(ChildDomNode->getBlock()); in findBestInsertionSet()
266 InsertPtsMap.reserve(Orders.size() + 1); in findBestInsertionSet()
267 for (auto RIt = Orders.rbegin(); RIt != Orders.rend(); RIt++) { in findBestInsertionSet()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h269 std::vector<SmallVector<Record*, 16> > Orders; variable
384 return Orders[No];
388 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
DCodeGenRegisters.cpp678 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
682 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
693 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
757 Orders.resize(Super.Orders.size()); in inheritProperties()
758 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
759 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
760 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
761 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.h296 std::vector<SmallVector<Record*, 16>> Orders; variable
431 return Orders[No];
435 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
DCodeGenRegisters.cpp760 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
765 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
777 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
849 Orders.resize(Super.Orders.size()); in inheritProperties()
850 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
851 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
852 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
853 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
/external/llvm-project/llvm/test/DebugInfo/X86/
Ddbg-value-transfer-order.ll24 ; with the Orders insertion point vector.
/external/llvm-project/llvm/include/llvm/CodeGen/
DFastISel.h563 DenseMap<MachineInstr *, unsigned> Orders; member
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DFastISel.h576 DenseMap<MachineInstr *, unsigned> Orders; member
/external/tensorflow/tensorflow/core/util/sparse/
DREADME.md192 conc_order = {1, 0} // Orders match along all inputs
/external/libtextclassifier/native/actions/
Dactions_model.fbs164 // Orders of charactergrams to extract, e.g. 2 means character bigrams, 3
/external/libtextclassifier/native/annotator/
Dmodel.fbs676 // Orders of charactergrams to extract. E.g., 2 means character bigrams, 3
/external/clang/lib/CodeGen/
DCGBuiltin.cpp1450 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
1464 Ptr, NewVal, Orders[i]); in EmitBuiltinExpr()
1516 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local
1526 Store->setOrdering(Orders[i]); in EmitBuiltinExpr()
/external/llvm-project/clang/lib/CodeGen/
DCGBuiltin.cpp3663 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
3677 Ptr, NewVal, Orders[i]); in EmitBuiltinExpr()
3729 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local
3739 Store->setOrdering(Orders[i]); in EmitBuiltinExpr()
/external/cldr/tools/java/org/unicode/cldr/util/data/
Deurope386 # Summer Time Act, 1925 and Summer Time Orders, 1926 and 1947:
/external/brotli/tests/testdata/
Dplrabn12.txt807 Each in his Hierarchy, the Orders bright.
8653 To those bright Orders uttered thus his voice.