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Searched refs:Orns (Results 1 – 8 of 8) sorted by relevance

/external/vixl/test/aarch32/
Dtest-disasm-a32.cc424 COMPARE_A32(Orns(r0, r0, 1), in TEST()
431 COMPARE_BOTH(Orns(r0, r1, 0x00ffffff), "orrs r0, r1, #0xff000000\n"); in TEST()
433 COMPARE_A32(Orns(r0, r1, 0xabcd2345), in TEST()
471 COMPARE_A32(Orns(r0, r0, Operand(r2, LSR, 2)), in TEST()
485 COMPARE_A32(Orns(r0, r0, Operand(r2, LSR, r3)), in TEST()
488 COMPARE_T32(Orns(r0, r0, Operand(r2, LSR, r3)), in TEST()
Dtest-simulator-cond-rd-rn-operand-rm-t32.cc127 M(Orns) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc127 M(Orns) \
Dtest-simulator-cond-rd-rn-operand-const-t32.cc127 M(Orns) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc127 M(Orns) \
Dtest-assembler-aarch32.cc3296 __ Orns(r0, r0, 0); in TEST() local
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.h2726 Orns(cond, rd, rn, operand); in Orn()
2740 void Orns(Condition cond, Register rd, Register rn, const Operand& operand) { in Orns() function
2750 void Orns(Register rd, Register rn, const Operand& operand) { in Orns() function
2751 Orns(al, rd, rn, operand); in Orns()
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.h5425 void Orns(const PRegisterWithLaneSize& pd, in Orns() function