| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 89 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); in shortenIIF() local
90 if (LiveRegs.contains(OtherReg)) in shortenIIF()
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 167 Register OtherReg = in getRegAllocationHints() local
169 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass) in getRegAllocationHints()
170 Worklist.push_back(OtherReg); in getRegAllocationHints()
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| D | SystemZShortenInst.cpp | 89 Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); in shortenIIF() local
90 if (LiveRegs.contains(OtherReg)) in shortenIIF()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 169 Register OtherReg = in getRegAllocationHints() local
171 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass) in getRegAllocationHints()
172 Worklist.push_back(OtherReg); in getRegAllocationHints()
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| D | SystemZShortenInst.cpp | 88 Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); in shortenIIF() local
89 if (LiveRegs.contains(OtherReg)) in shortenIIF()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 321 unsigned OtherReg = Hint.second; in updateRegAllocHint() local
322 Hint = MRI->getRegAllocationHint(OtherReg); in updateRegAllocHint()
325 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
329 : ARMRI::RegPairOdd, OtherReg); in updateRegAllocHint()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 366 unsigned OtherReg = Hint.second; in updateRegAllocHint() local
367 Hint = MRI->getRegAllocationHint(OtherReg); in updateRegAllocHint()
370 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
374 : ARMRI::RegPairOdd, OtherReg); in updateRegAllocHint()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 383 Register OtherReg = Hint.second; in updateRegAllocHint() local
384 Hint = MRI->getRegAllocationHint(OtherReg); in updateRegAllocHint()
387 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
393 OtherReg); in updateRegAllocHint()
|
| /external/llvm/lib/CodeGen/ |
| D | RegAllocGreedy.cpp | 2322 unsigned OtherReg = Instr.getOperand(0).getReg(); in collectHintInfo() local
2323 if (OtherReg == Reg) { in collectHintInfo()
2324 OtherReg = Instr.getOperand(1).getReg(); in collectHintInfo()
2325 if (OtherReg == Reg) in collectHintInfo()
2329 unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg) in collectHintInfo()
2330 ? OtherReg in collectHintInfo()
2331 : VRM->getPhys(OtherReg); in collectHintInfo()
2333 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg, in collectHintInfo()
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| D | RegisterCoalescer.cpp | 2860 unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg; in applyTerminalRule() local
2861 isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg, in applyTerminalRule()
2863 if (OtherReg == SrcReg) in applyTerminalRule()
2864 OtherReg = OtherSrcReg; in applyTerminalRule()
2866 if (TargetRegisterInfo::isPhysicalRegister(OtherReg) || in applyTerminalRule()
2867 isTerminalReg(OtherReg, MI, MRI)) in applyTerminalRule()
2870 if (LIS->getInterval(OtherReg).overlaps(DstLI)) { in applyTerminalRule()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegAllocGreedy.cpp | 2877 Register OtherReg = Instr.getOperand(0).getReg(); in collectHintInfo() local
2878 if (OtherReg == Reg) { in collectHintInfo()
2879 OtherReg = Instr.getOperand(1).getReg(); in collectHintInfo()
2880 if (OtherReg == Reg) in collectHintInfo()
2884 Register OtherPhysReg = Register::isPhysicalRegister(OtherReg) in collectHintInfo()
2885 ? OtherReg in collectHintInfo()
2886 : VRM->getPhys(OtherReg); in collectHintInfo()
2888 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg, in collectHintInfo()
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| D | RegisterCoalescer.cpp | 3728 unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg; in applyTerminalRule() local
3729 if (!isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg, in applyTerminalRule()
3732 if (OtherReg == SrcReg) in applyTerminalRule()
3733 OtherReg = OtherSrcReg; in applyTerminalRule()
3735 if (Register::isPhysicalRegister(OtherReg) || in applyTerminalRule()
3736 isTerminalReg(OtherReg, MI, MRI)) in applyTerminalRule()
3739 if (LIS->getInterval(OtherReg).overlaps(DstLI)) { in applyTerminalRule()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegAllocGreedy.cpp | 2867 Register OtherReg = Instr.getOperand(0).getReg(); in collectHintInfo() local
2868 if (OtherReg == Reg) { in collectHintInfo()
2869 OtherReg = Instr.getOperand(1).getReg(); in collectHintInfo()
2870 if (OtherReg == Reg) in collectHintInfo()
2875 OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg); in collectHintInfo()
2877 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg, in collectHintInfo()
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| D | RegisterCoalescer.cpp | 3751 Register OtherSrcReg, OtherReg; in applyTerminalRule() local
3753 if (!isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg, in applyTerminalRule()
3756 if (OtherReg == SrcReg) in applyTerminalRule()
3757 OtherReg = OtherSrcReg; in applyTerminalRule()
3759 if (Register::isPhysicalRegister(OtherReg) || in applyTerminalRule()
3760 isTerminalReg(OtherReg, MI, MRI)) in applyTerminalRule()
3763 if (LIS->getInterval(OtherReg).overlaps(DstLI)) { in applyTerminalRule()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 1037 &Optimized](Register &Reg, Register &OtherReg, in emitSelect()
1055 std::swap(Reg, OtherReg); in emitSelect()
1072 std::swap(Reg, OtherReg); in emitSelect()
1089 std::swap(Reg, OtherReg); in emitSelect()
|