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Searched refs:OutMI (Results 1 – 25 of 99) sorted by relevance

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/external/llvm/lib/Target/Mips/
DMipsMCInstLower.cpp216 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { in lowerLongBranchLUi()
217 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
220 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
223 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), in lowerLongBranchLUi()
229 const MachineInstr *MI, MCInst &OutMI, int Opcode, in lowerLongBranchADDiu() argument
231 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
236 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
240 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), in lowerLongBranchADDiu()
245 MCInst &OutMI) const { in lowerLongBranch()
250 lowerLongBranchLUi(MI, OutMI); in lowerLongBranch()
[all …]
DMipsMCInstLower.h33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
41 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
42 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
44 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
389 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
390 OutMI.setOpcode(MI->getOpcode()); in Lower()
394 OutMI.addOperand(MaybeMCOp.getValue()); in Lower()
398 switch (OutMI.getOpcode()) { in Lower()
404 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
406 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
425 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && in Lower()
426 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { in Lower()
428 switch (OutMI.getOpcode()) { in Lower()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMCInstLower.cpp215 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { in lowerLongBranchLUi()
216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
219 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
244 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); in lowerLongBranchLUi()
247 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), in lowerLongBranchLUi()
253 MCInst &OutMI, int Opcode) const { in lowerLongBranchADDiu() argument
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
278 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
286 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); in lowerLongBranchADDiu()
289 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), in lowerLongBranchADDiu()
[all …]
DMipsMCInstLower.h37 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
45 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
46 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
48 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMCInstLower.cpp215 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { in lowerLongBranchLUi()
216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
219 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
244 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); in lowerLongBranchLUi()
247 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), in lowerLongBranchLUi()
253 MCInst &OutMI, int Opcode) const { in lowerLongBranchADDiu() argument
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
278 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
286 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); in lowerLongBranchADDiu()
289 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), in lowerLongBranchADDiu()
[all …]
DMipsMCInstLower.h37 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
45 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
46 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
48 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyMCInstLower.cpp44 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI);
213 MCInst &OutMI) const { in lower()
214 OutMI.setOpcode(MI->getOpcode()); in lower()
318 OutMI.addOperand(MCOp); in lower()
322 removeRegisterOperands(MI, OutMI); in lower()
324 OutMI.insert(OutMI.begin(), MCOperand::createImm(MI->getNumExplicitDefs())); in lower()
327 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) { in removeRegisterOperands() argument
345 auto RegOpcode = OutMI.getOpcode(); in removeRegisterOperands()
348 OutMI.setOpcode(StackOpcode); in removeRegisterOperands()
351 for (auto I = OutMI.getNumOperands(); I; --I) { in removeRegisterOperands()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUMCInstLower.cpp56 void lower(const MachineInstr *MI, MCInst &OutMI) const;
66 void lower(const MachineInstr *MI, MCInst &OutMI) const;
176 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower()
192 OutMI.addOperand(Dest); in lower()
193 OutMI.addOperand(Src); in lower()
207 OutMI.setOpcode(MCOpcode); in lower()
212 OutMI.addOperand(MCOp); in lower()
216 if (FIIdx >= (int)OutMI.getNumOperands()) in lower()
217 OutMI.addOperand(MCOperand::createImm(0)); in lower()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyMCInstLower.cpp45 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI);
207 MCInst &OutMI) const { in lower()
208 OutMI.setOpcode(MI->getOpcode()); in lower()
304 OutMI.addOperand(MCOp); in lower()
308 removeRegisterOperands(MI, OutMI); in lower()
311 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) { in removeRegisterOperands() argument
329 auto RegOpcode = OutMI.getOpcode(); in removeRegisterOperands()
332 OutMI.setOpcode(StackOpcode); in removeRegisterOperands()
335 for (auto I = OutMI.getNumOperands(); I; --I) { in removeRegisterOperands()
336 auto &MO = OutMI.getOperand(I - 1); in removeRegisterOperands()
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/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVMCInstLower.cpp130 MCInst &OutMI) { in lowerRISCVVMachineInstrToMCInst() argument
136 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
185 OutMI.addOperand(MCOp); in lowerRISCVVMachineInstrToMCInst()
190 void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerRISCVMachineInstrToMCInst() argument
192 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI)) in LowerRISCVMachineInstrToMCInst()
195 OutMI.setOpcode(MI->getOpcode()); in LowerRISCVMachineInstrToMCInst()
200 OutMI.addOperand(MCOp); in LowerRISCVMachineInstrToMCInst()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUMCInstLower.cpp56 void lower(const MachineInstr *MI, MCInst &OutMI) const;
66 void lower(const MachineInstr *MI, MCInst &OutMI) const;
176 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower()
192 OutMI.addOperand(Dest); in lower()
193 OutMI.addOperand(Src); in lower()
207 OutMI.setOpcode(MCOpcode); in lower()
212 OutMI.addOperand(MCOp); in lower()
216 if (FIIdx >= (int)OutMI.getNumOperands()) in lower()
217 OutMI.addOperand(MCOperand::createImm(0)); in lower()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86MCInstLower.cpp66 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
492 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
493 OutMI.setOpcode(MI->getOpcode()); in Lower()
497 OutMI.addOperand(MaybeMCOp.getValue()); in Lower()
500 switch (OutMI.getOpcode()) { in Lower()
506 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands && in Lower()
508 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && in Lower()
518 switch (OutMI.getOpcode()) { in Lower()
525 OutMI.setOpcode(NewOpc); in Lower()
527 unsigned DestReg = OutMI.getOperand(0).getReg(); in Lower()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
465 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
466 OutMI.setOpcode(MI->getOpcode()); in Lower()
470 OutMI.addOperand(MaybeMCOp.getValue()); in Lower()
473 switch (OutMI.getOpcode()) { in Lower()
479 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands && in Lower()
481 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && in Lower()
500 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && in Lower()
501 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { in Lower()
503 switch (OutMI.getOpcode()) { in Lower()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64MCInstLower.cpp296 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
297 OutMI.setOpcode(MI->getOpcode()); in Lower()
302 OutMI.addOperand(MCOp); in Lower()
305 switch (OutMI.getOpcode()) { in Lower()
307 OutMI = MCInst(); in Lower()
308 OutMI.setOpcode(AArch64::RET); in Lower()
309 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
312 OutMI = MCInst(); in Lower()
313 OutMI.setOpcode(AArch64::RET); in Lower()
314 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64MCInstLower.cpp296 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
297 OutMI.setOpcode(MI->getOpcode()); in Lower()
302 OutMI.addOperand(MCOp); in Lower()
305 switch (OutMI.getOpcode()) { in Lower()
307 OutMI = MCInst(); in Lower()
308 OutMI.setOpcode(AArch64::RET); in Lower()
309 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
312 OutMI = MCInst(); in Lower()
313 OutMI.setOpcode(AArch64::RET); in Lower()
314 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEMCInstLower.cpp58 void llvm::LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerVEMachineInstrToMCInst() argument
60 OutMI.setOpcode(MI->getOpcode()); in LowerVEMachineInstrToMCInst()
67 OutMI.addOperand(MCOp); in LowerVEMachineInstrToMCInst()
/external/llvm/lib/Target/BPF/
DBPFMCInstLower.cpp43 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
44 OutMI.setOpcode(MI->getOpcode()); in Lower()
74 OutMI.addOperand(MCOp); in Lower()
/external/llvm-project/llvm/lib/Target/BPF/
DBPFMCInstLower.cpp47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
48 OutMI.setOpcode(MI->getOpcode()); in Lower()
81 OutMI.addOperand(MCOp); in Lower()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFMCInstLower.cpp47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
48 OutMI.setOpcode(MI->getOpcode()); in Lower()
81 OutMI.addOperand(MCOp); in Lower()
/external/llvm/lib/Target/Sparc/
DSparcMCInstLower.cpp95 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
99 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
106 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcMCInstLower.cpp94 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
98 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
105 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcMCInstLower.cpp94 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
98 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
105 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyMCInstLower.cpp58 MCInst &OutMI) const { in Lower()
59 OutMI.setOpcode(MI->getOpcode()); in Lower()
113 OutMI.addOperand(MCOp); in Lower()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZMCInstLower.cpp94 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
95 OutMI.setOpcode(MI->getOpcode()); in lower()
100 OutMI.addOperand(lowerOperand(MO)); in lower()

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