| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 293 SDValue OutVal = OutVals[i]; in LowerReturn() local
300 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
303 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
306 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
319 OutVal = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, in LowerReturn()
320 MVT::i64, Undef, OutVal, Sub_f32), in LowerReturn()
330 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 312 SDValue &OutVal = OutVals[i]; in LowerCall() local
330 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(), in LowerCall()
333 OutVal = FINode; in LowerCall()
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 317 SDValue OutVal = OutVals[i]; in LowerReturn_64() local
323 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
326 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
329 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
338 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
345 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 317 SDValue OutVal = OutVals[i]; in LowerReturn_64() local
323 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
326 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
329 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
338 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
345 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 319 SDValue OutVal = OutVals[i]; in LowerReturn_64() local
325 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
331 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
340 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
347 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
353 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
|
| /external/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| D | InstrRefBasedImpl.cpp | 2550 const DbgValue &OutVal = It->second; in pickVPHILoc() local
2552 if (OutVal.Kind == DbgValue::Const || OutVal.Kind == DbgValue::NoVal) in pickVPHILoc()
2556 assert(OutVal.Kind == DbgValue::Proposed || OutVal.Kind == DbgValue::Def); in pickVPHILoc()
2557 ValueIDNum ValToLookFor = OutVal.ID; in pickVPHILoc()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1601 SDValue OutVal = N->getOperand(3); in PerformDAGCombine() local
1603 if (OutVal.hasOneUse()) { in PerformDAGCombine()
1604 unsigned BitWidth = OutVal.getValueSizeInBits(); in PerformDAGCombine()
1610 if (TLI.ShrinkDemandedConstant(OutVal, DemandedMask, TLO) || in PerformDAGCombine()
1611 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO)) in PerformDAGCombine()
|
| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1600 SDValue OutVal = N->getOperand(3); in PerformDAGCombine() local
1602 if (OutVal.hasOneUse()) { in PerformDAGCombine()
1603 unsigned BitWidth = OutVal.getValueSizeInBits(); in PerformDAGCombine()
1609 if (TLI.ShrinkDemandedConstant(OutVal, DemandedMask, TLO) || in PerformDAGCombine()
1610 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO)) in PerformDAGCombine()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1613 SDValue OutVal = N->getOperand(3); in PerformDAGCombine() local
1615 if (OutVal.hasOneUse()) { in PerformDAGCombine()
1616 unsigned BitWidth = OutVal.getValueSizeInBits(); in PerformDAGCombine()
1622 if (TLO.ShrinkDemandedConstant(OutVal, DemandedMask) || in PerformDAGCombine()
1623 TLI.SimplifyDemandedBits(OutVal, DemandedMask, KnownZero, KnownOne, in PerformDAGCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 723 SDValue &OutVal = OutVals[I]; in LowerCall() local
741 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(), in LowerCall()
744 OutVal = FINode; in LowerCall()
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 870 SDValue &OutVal = OutVals[I]; in LowerCall() local
890 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getNonZeroByValAlign(), in LowerCall()
893 OutVal = FINode; in LowerCall()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 7077 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), in visitInlineAsm() local
7079 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); in visitInlineAsm()
|