| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | machine-outliner-retaddr-sign-sp-mod.mir | 70 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
90 # CHECK: frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
103 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
123 # CHECK: frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
136 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
159 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
179 # CHECK: frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
189 # CHECK: frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
201 # CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp
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| D | branch-target-enforcement.mir | 130 # Function starts with PACIASP, which implicitly acts as BTI JC, so no change
143 ; CHECK: frame-setup PACIASP
146 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
317 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
339 # When PACIASP is the first real instruction in the functions then BTI should not be inserted.
351 ; CHECK: frame-setup PACIASP
354 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
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| /external/arm-optimized-routines/string/ |
| D | asmdefs.h | 17 #define PACIASP hint 25; .cfi_window_save macro
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| /external/llvm-project/llvm/test/CodeGen/MIR/AArch64/ |
| D | return-address-signing.mir | 23 #CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64BranchTargets.cpp | 129 (MBBI->getOpcode() == AArch64::PACIASP || in addBTI()
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| D | AArch64FrameLowering.cpp | 1062 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP)) in emitPrologue()
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| D | AArch64InstrInfo.cpp | 6483 case AArch64::PACIASP: in getOutliningType()
6679 BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIASP)) in signOutlinedFunction()
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| D | AArch64InstrInfo.td | 951 def PACIASP : SystemNoOperands<0b001, "hint\t#25">;
979 def : InstAlias<"paciasp", (PACIASP), 0>;
997 def : InstAlias<"paciasp", (PACIASP), 1>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64BranchTargets.cpp | 122 if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP || in addBTI()
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| D | AArch64FrameLowering.cpp | 887 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP)) in emitPrologue()
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| D | AArch64InstrInfo.cpp | 6070 case AArch64::PACIASP: in getOutliningType()
6253 BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIASP)) in signOutlinedFunction()
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| D | AArch64InstrInfo.td | 837 def PACIASP : SystemNoOperands<0b001, "hint #25">;
865 def : InstAlias<"paciasp", (PACIASP), 1>;
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| /external/vixl/src/aarch64/ |
| D | cpu-features-auditor-aarch64.cc | 1239 case PACIASP: in VIXL_SIMPLE_SVE_VISITOR_LIST()
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| D | constants-aarch64.h | 980 PACIASP = SystemPAuthFixed | 0x00000320, enumerator
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| D | simulator-aarch64.h | 1144 if ((i != PACIASP) && (i != PACIBSP)) {
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| D | disasm-aarch64.cc | 2118 V(PACIASP, "paciasp") \
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| D | assembler-aarch64.cc | 2629 Emit(PACIASP); in paciasp()
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| D | simulator-aarch64.cc | 4487 if ((i == PACIASP) || (i == PACIBSP)) { in VisitSystem()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmWriter.inc | 3872 7042U, // PACIASP
9262 0U, // PACIASP
15304 {AArch64::PACIASP, 569, 1 },
16637 // AArch64::PACIASP - 569
20241 // (PACIASP) - 2428
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| D | AArch64GenAsmWriter1.inc | 4869 17393U, // PACIASP
10259 0U, // PACIASP
16025 {AArch64::PACIASP, 569, 1 },
17358 // AArch64::PACIASP - 569
20962 // (PACIASP) - 2428
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| D | AArch64GenMCCodeEmitter.inc | 2923 UINT64_C(3573752639), // PACIASP
5474 case AArch64::PACIASP:
18852 CEFBS_None, // PACIASP = 2910
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| D | AArch64GenAsmMatcher.inc | 14672 { 1765 /* hint */, AArch64::PACIASP, Convert_NoOperands, AMFBS_None, { MCK__HASH_25 }, },
16883 { 3556 /* paciasp */, AArch64::PACIASP, Convert_NoOperands, AMFBS_HasPA, { }, },
22045 { 1765 /* hint */, AArch64::PACIASP, Convert_NoOperands, AMFBS_None, { MCK__HASH_25 }, },
24256 { 3556 /* paciasp */, AArch64::PACIASP, Convert_NoOperands, AMFBS_HasPA, { }, },
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| D | AArch64GenInstrInfo.inc | 2925 PACIASP = 2910,
9809 …ideEffects), 0x1ULL, ImplicitList5, ImplicitList6, nullptr, -1 ,nullptr }, // Inst #2910 = PACIASP
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| D | AArch64GenDisassemblerTables.inc | 16890 /* 82107 */ MCD::OPC_Decode, 222, 22, 107, // Opcode: PACIASP
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2122 ### PACIASP ### subsection
|