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Searched refs:PHY_REG (Results 1 – 4 of 4) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c151 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
159 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1) in select_per_cs_training_index()
172 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, in override_write_leveling_value()
174 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
198 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
238 obs_0 = mmio_read_32(PHY_REG(ch, 532)); in data_training()
239 obs_1 = mmio_read_32(PHY_REG(ch, 660)); in data_training()
240 obs_2 = mmio_read_32(PHY_REG(ch, 788)); in data_training()
280 obs_0 = mmio_read_32(PHY_REG(ch, 40)); in data_training()
281 obs_1 = mmio_read_32(PHY_REG(ch, 168)); in data_training()
[all …]
Ddfs.c218 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; in sdram_timing_cfg_init()
1400 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1401 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1402 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1403 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1405 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1406 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1407 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1408 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1432 mmio_setbits_32(PHY_REG(ch, 514), 1); in gen_rk3399_phy_dll_bypass()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c60 mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
/external/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
Daddressmap_shared.h100 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) macro