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Searched refs:PIPE_CONTROL_CACHE_FLUSH_BITS (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c62 if ((flags & PIPE_CONTROL_CACHE_FLUSH_BITS) && in iris_emit_pipe_control_flush()
76 flags & PIPE_CONTROL_CACHE_FLUSH_BITS); in iris_emit_pipe_control_flush()
77 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL); in iris_emit_pipe_control_flush()
187 const uint32_t all_flush_bits = (PIPE_CONTROL_CACHE_FLUSH_BITS | in iris_emit_buffer_barrier_for()
270 if (bits & PIPE_CONTROL_CACHE_FLUSH_BITS) in iris_emit_buffer_barrier_for()
Diris_context.h324 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro
Diris_state.c7102 if ((flags & (PIPE_CONTROL_CACHE_FLUSH_BITS | in batch_mark_sync_for_pipe_control()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c42 (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) && in brw_emit_pipe_control_flush()
55 brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS)); in brw_emit_pipe_control_flush()
56 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL); in brw_emit_pipe_control_flush()
Dbrw_pipe_control.h68 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro