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Searched refs:PIPE_CONTROL_CACHE_INVALIDATE_BITS (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h72 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro
Dbrw_pipe_control.c43 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in brw_emit_pipe_control_flush()
/external/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c63 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in iris_emit_pipe_control_flush()
Diris_context.h329 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro