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Searched refs:PIPE_CONTROL_CONST_CACHE_INVALIDATE (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h62 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21), enumerator
73 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
Dbrw_pipe_control.c364 PIPE_CONTROL_CONST_CACHE_INVALIDATE | in brw_emit_mi_flush()
DgenX_pipe_control.c486 flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE; in genX()
Dgen7_l3_state.c107 PIPE_CONTROL_CONST_CACHE_INVALIDATE | in setup_l3_config()
Dbrw_misc_state.c539 PIPE_CONTROL_CONST_CACHE_INVALIDATE | in brw_emit_select_pipeline()
Dbrw_program.c361 PIPE_CONTROL_CONST_CACHE_INVALIDATE); in brw_memory_barrier()
Dintel_fbo.c1028 PIPE_CONTROL_CONST_CACHE_INVALIDATE); in flush_depth_and_render_caches()
/external/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c201 PIPE_CONTROL_CONST_CACHE_INVALIDATE), in iris_emit_buffer_barrier_for()
298 PIPE_CONTROL_CONST_CACHE_INVALIDATE | in iris_flush_all_caches()
346 PIPE_CONTROL_CONST_CACHE_INVALIDATE; in iris_memory_barrier()
Diris_context.h316 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21), enumerator
331 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
Diris_state.c469 PIPE_CONTROL_CONST_CACHE_INVALIDATE | in flush_after_state_base_change()
664 PIPE_CONTROL_CONST_CACHE_INVALIDATE | in emit_pipeline_select()
7117 (flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE)) in batch_mark_sync_for_pipe_control()
7528 (flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE) ? "Const " : "", in iris_emit_raw_pipe_control()
7576 flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE; in iris_emit_raw_pipe_control()
Diris_resource.c2144 flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; in iris_flush_bits_for_history()
/external/igt-gpu-tools/tests/
Dperf.c78 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3) macro