| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | genX_pipe_control.c | 132 genX(emit_raw_pipe_control)(brw, PIPE_CONTROL_CS_STALL, NULL, 0, 0); in genX()
230 flags |= PIPE_CONTROL_CS_STALL; in genX()
289 flags |= PIPE_CONTROL_CS_STALL; in genX()
340 flags |= PIPE_CONTROL_CS_STALL; in genX()
354 flags |= PIPE_CONTROL_CS_STALL; in genX()
379 flags |= PIPE_CONTROL_CS_STALL; in genX()
411 if (flags & PIPE_CONTROL_CS_STALL) { in genX()
419 flags |= PIPE_CONTROL_CS_STALL; in genX()
428 if (GEN_GEN < 9 && (flags & PIPE_CONTROL_CS_STALL)) { in genX()
473 pc.CommandStreamerStallEnable = flags & PIPE_CONTROL_CS_STALL; in genX()
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| D | brw_pipe_control.c | 56 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL); in brw_emit_pipe_control_flush()
173 PIPE_CONTROL_CS_STALL, in gen7_emit_isp_disable()
177 PIPE_CONTROL_CS_STALL, in gen7_emit_isp_disable()
194 PIPE_CONTROL_CS_STALL in gen7_emit_cs_stall_flush()
241 PIPE_CONTROL_CS_STALL | in brw_emit_post_sync_nonzero_flush()
302 flags | PIPE_CONTROL_CS_STALL | in brw_emit_end_of_pipe_sync()
369 PIPE_CONTROL_CS_STALL; in brw_emit_mi_flush()
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| D | brw_queryobj.c | 84 PIPE_CONTROL_CS_STALL | in brw_write_timestamp()
91 flags |= PIPE_CONTROL_CS_STALL; in brw_write_timestamp()
107 flags |= PIPE_CONTROL_CS_STALL; in brw_write_depth_count()
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| D | brw_pipe_control.h | 45 PIPE_CONTROL_CS_STALL = (1 << 4), enumerator
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| D | gen7_l3_state.c | 89 PIPE_CONTROL_CS_STALL); in setup_l3_config()
116 PIPE_CONTROL_CS_STALL); in setup_l3_config()
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| D | gen8_depth_state.c | 151 PIPE_CONTROL_CS_STALL | in gen8_write_pma_stall_bits()
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| D | brw_blorp.c | 524 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
534 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
1618 PIPE_CONTROL_CS_STALL); in intel_hiz_exec()
1643 PIPE_CONTROL_CS_STALL); in intel_hiz_exec()
1676 PIPE_CONTROL_CS_STALL); in intel_hiz_exec()
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| D | brw_misc_state.c | 535 PIPE_CONTROL_CS_STALL); in brw_emit_select_pipeline()
685 PIPE_CONTROL_CS_STALL); in brw_emit_hashing_mode()
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| D | intel_tex.c | 316 PIPE_CONTROL_CS_STALL); in intel_texture_barrier()
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| D | genX_blorp_exec.c | 229 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL); in blorp_vf_invalidate_for_vb_48b_transitions()
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| D | gen6_queryobj.c | 69 flags |= PIPE_CONTROL_CS_STALL; in set_query_availability()
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| D | brw_program.c | 351 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL; in brw_memory_barrier()
394 PIPE_CONTROL_CS_STALL); in brw_framebuffer_fetch_barrier()
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| D | hsw_queryobj.c | 293 PIPE_CONTROL_CS_STALL | in hsw_result_to_gpr0()
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| D | intel_fbo.c | 1024 PIPE_CONTROL_CS_STALL); in flush_depth_and_render_caches()
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| D | brw_draw.c | 442 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); in gen9_apply_astc5x5_wa_flush()
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| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_pipe_control.c | 77 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL); in iris_emit_pipe_control_flush()
149 flags | PIPE_CONTROL_CS_STALL | in iris_emit_end_of_pipe_sync()
291 PIPE_CONTROL_CS_STALL | in iris_flush_all_caches()
315 PIPE_CONTROL_CS_STALL); in iris_texture_barrier()
325 PIPE_CONTROL_CS_STALL); in iris_texture_barrier()
336 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL; in iris_memory_barrier()
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| D | iris_fine_fence.c | 65 pc = PIPE_CONTROL_WRITE_IMMEDIATE | PIPE_CONTROL_CS_STALL; in iris_fine_fence_new()
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| D | iris_query.c | 159 GEN_GEN == 9 && devinfo->gt == 4 ? PIPE_CONTROL_CS_STALL : 0; in iris_pipelined_write()
176 PIPE_CONTROL_CS_STALL | in write_value()
253 PIPE_CONTROL_CS_STALL | in write_overflow_values()
706 PIPE_CONTROL_CS_STALL); in iris_get_query_result_resource()
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| D | iris_state.c | 659 PIPE_CONTROL_CS_STALL); in emit_pipeline_select()
1617 PIPE_CONTROL_CS_STALL | in genX()
5307 PIPE_CONTROL_CS_STALL); in genX()
6273 PIPE_CONTROL_CS_STALL; in iris_upload_dirty_render_state()
6511 PIPE_CONTROL_CS_STALL); in iris_upload_render_state()
6624 PIPE_CONTROL_CS_STALL); in iris_upload_render_state()
6727 PIPE_CONTROL_CS_STALL); in iris_upload_gpgpu_walker()
7092 if ((flags & PIPE_CONTROL_CS_STALL)) { in batch_mark_sync_for_pipe_control()
7212 PIPE_CONTROL_CS_STALL | in iris_emit_raw_pipe_control()
7232 PIPE_CONTROL_CS_STALL, bo, offset, imm); in iris_emit_raw_pipe_control()
[all …]
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| D | iris_blorp.c | 222 PIPE_CONTROL_CS_STALL); in blorp_vf_invalidate_for_vb_48b_transitions()
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| D | iris_blit.c | 318 iris_emit_pipe_control_flush(batch, reason, PIPE_CONTROL_CS_STALL); in tex_cache_flush_hack()
788 PIPE_CONTROL_CS_STALL); in iris_resource_copy_region()
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| D | iris_resolve.c | 379 PIPE_CONTROL_CS_STALL); in iris_cache_flush_for_render()
559 PIPE_CONTROL_CS_STALL); in iris_hiz_exec()
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| D | iris_context.h | 299 PIPE_CONTROL_CS_STALL = (1 << 4), enumerator
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| D | iris_resource.c | 1436 PIPE_CONTROL_CS_STALL); in iris_map_copy_region()
1993 if (history_flush & ~PIPE_CONTROL_CS_STALL) { in iris_transfer_flush_region()
2141 uint32_t flush = PIPE_CONTROL_CS_STALL; in iris_flush_bits_for_history()
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| /external/igt-gpu-tools/tests/i915/ |
| D | gem_pipe_control_store_loop.c | 60 #define PIPE_CONTROL_CS_STALL (1<<20) macro
115 OUT_BATCH(PIPE_CONTROL_CS_STALL | in store_pipe_control_loop()
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