Searched refs:PIPE_CONTROL_DATA_CACHE_FLUSH (Results 1 – 11 of 11) sorted by relevance
60 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), enumerator69 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
362 PIPE_CONTROL_DATA_CACHE_FLUSH)))) { in genX()455 PIPE_CONTROL_DATA_CACHE_FLUSH; in genX()469 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH; in genX()
88 PIPE_CONTROL_DATA_CACHE_FLUSH | in setup_l3_config()115 PIPE_CONTROL_DATA_CACHE_FLUSH | in setup_l3_config()
365 PIPE_CONTROL_DATA_CACHE_FLUSH | in brw_emit_mi_flush()
529 devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; in brw_emit_select_pipeline()759 devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; in brw_upload_state_base_address()
351 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL; in brw_memory_barrier()
292 PIPE_CONTROL_DATA_CACHE_FLUSH | in iris_flush_all_caches()336 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL; in iris_memory_barrier()
70 PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_fine_fence_new()
314 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), enumerator326 PIPE_CONTROL_DATA_CACHE_FLUSH | \
2147 PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_flush_bits_for_history()2157 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_flush_bits_for_history()
412 PIPE_CONTROL_DATA_CACHE_FLUSH | in flush_before_state_base_change()658 PIPE_CONTROL_DATA_CACHE_FLUSH | in emit_pipeline_select()7437 PIPE_CONTROL_DATA_CACHE_FLUSH)))) { in iris_emit_raw_pipe_control()7504 PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_emit_raw_pipe_control()7530 (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "", in iris_emit_raw_pipe_control()7561 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_emit_raw_pipe_control()