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Searched refs:PIPE_CONTROL_FLUSH_ENABLE (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c189 PIPE_CONTROL_FLUSH_ENABLE); in iris_emit_buffer_barrier_for()
193 [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, in iris_emit_buffer_barrier_for()
199 [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, in iris_emit_buffer_barrier_for()
Diris_query.c142 flags |= PIPE_CONTROL_FLUSH_ENABLE; in mark_available()
780 PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_result()
Diris_context.h313 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18), enumerator
Diris_state.c4672 PIPE_CONTROL_FLUSH_ENABLE | in surf_state_update_clear_value()
6535 PIPE_CONTROL_FLUSH_ENABLE); in iris_upload_render_state()
7099 if ((flags & PIPE_CONTROL_FLUSH_ENABLE)) in batch_mark_sync_for_pipe_control()
7113 if ((flags & PIPE_CONTROL_FLUSH_ENABLE)) in batch_mark_sync_for_pipe_control()
7523 (flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "", in iris_emit_raw_pipe_control()
7560 pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE; in iris_emit_raw_pipe_control()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_conditional_render.c65 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_overflow_query()
87 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_occlusion_query()
Dbrw_pipe_control.h59 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18), enumerator
DgenX_pipe_control.c468 pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE; in genX()
Dgen6_queryobj.c66 flags |= PIPE_CONTROL_FLUSH_ENABLE; in set_query_availability()
Dbrw_draw.c1196 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in brw_draw_prims()
/external/igt-gpu-tools/tests/
Dperf.c74 #define PIPE_CONTROL_FLUSH_ENABLE (1 << 7) /* Gen7+ only */ macro