Home
last modified time | relevance | path

Searched refs:PIPE_CONTROL_RENDER_TARGET_FLUSH (Results 1 – 23 of 23) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
DgenX_pipe_control.c97 if (GEN_GEN == 6 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) { in genX()
161 assert(!(flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH | in genX()
189 if (flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH | in genX()
217 PIPE_CONTROL_RENDER_TARGET_FLUSH))); in genX()
360 PIPE_CONTROL_RENDER_TARGET_FLUSH | in genX()
448 const uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH | in genX()
480 flags & PIPE_CONTROL_RENDER_TARGET_FLUSH; in genX()
488 pc.WriteCacheFlush = flags & PIPE_CONTROL_RENDER_TARGET_FLUSH; in genX()
Dbrw_pipe_control.h54 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13), enumerator
70 PIPE_CONTROL_RENDER_TARGET_FLUSH)
Dbrw_program.c369 PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_memory_barrier()
373 PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_memory_barrier()
379 bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH; in brw_memory_barrier()
393 PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_framebuffer_fetch_barrier()
399 PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_framebuffer_fetch_barrier()
Dgen8_depth_state.c149 brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0; in gen8_write_pma_stall_bits()
Dbrw_pipe_control.c361 int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH; in brw_emit_mi_flush()
Dbrw_blorp.c1308 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in do_single_blorp_clear()
1317 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in do_single_blorp_clear()
1527 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_blorp_resolve_color()
1538 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_blorp_resolve_color()
1616 PIPE_CONTROL_RENDER_TARGET_FLUSH | in intel_hiz_exec()
Dbrw_misc_state.c532 PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_emit_select_pipeline()
783 PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_upload_state_base_address()
Dintel_tex.c315 PIPE_CONTROL_RENDER_TARGET_FLUSH | in intel_texture_barrier()
DgenX_blorp_exec.c301 PIPE_CONTROL_RENDER_TARGET_FLUSH | in genX()
Dbrw_state_upload.c59 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_enable_obj_preemption()
Dintel_fbo.c1023 PIPE_CONTROL_RENDER_TARGET_FLUSH | in flush_depth_and_render_caches()
Dintel_batchbuffer.c641 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_finish_batch()
Dbrw_wm_surface_state.c1043 PIPE_CONTROL_RENDER_TARGET_FLUSH | in update_renderbuffer_surfaces()
/external/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c191 [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH, in iris_emit_buffer_barrier_for()
197 [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH, in iris_emit_buffer_barrier_for()
294 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_flush_all_caches()
314 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_texture_barrier()
351 PIPE_CONTROL_RENDER_TARGET_FLUSH; in iris_memory_barrier()
Diris_fine_fence.c68 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_fine_fence_new()
Diris_clear.c305 PIPE_CONTROL_RENDER_TARGET_FLUSH); in fast_clear_color()
328 PIPE_CONTROL_RENDER_TARGET_FLUSH); in fast_clear_color()
405 PIPE_CONTROL_RENDER_TARGET_FLUSH, in clear_color()
Diris_context.h308 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13), enumerator
327 PIPE_CONTROL_RENDER_TARGET_FLUSH)
Diris_resolve.c378 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_cache_flush_for_render()
412 PIPE_CONTROL_RENDER_TARGET_FLUSH); in iris_resolve_color()
431 PIPE_CONTROL_RENDER_TARGET_FLUSH); in iris_resolve_color()
Diris_blorp.c273 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_blorp_exec()
Diris_blit.c591 PIPE_CONTROL_RENDER_TARGET_FLUSH, in iris_blit()
808 PIPE_CONTROL_RENDER_TARGET_FLUSH, in iris_resource_copy_region()
Diris_state.c410 PIPE_CONTROL_RENDER_TARGET_FLUSH | in flush_before_state_base_change()
656 PIPE_CONTROL_RENDER_TARGET_FLUSH | in emit_pipeline_select()
794 PIPE_CONTROL_RENDER_TARGET_FLUSH); in iris_enable_obj_preemption()
1619 PIPE_CONTROL_RENDER_TARGET_FLUSH); in genX()
1640 PIPE_CONTROL_RENDER_TARGET_FLUSH); in genX()
5755 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_upload_dirty_render_state()
7093 if ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) in batch_mark_sync_for_pipe_control()
7107 if ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) in batch_mark_sync_for_pipe_control()
7270 if (flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_emit_raw_pipe_control()
7298 PIPE_CONTROL_RENDER_TARGET_FLUSH))); in iris_emit_raw_pipe_control()
[all …]
Diris_resource.c1435 PIPE_CONTROL_RENDER_TARGET_FLUSH | in iris_map_copy_region()
1985 history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH; in iris_transfer_flush_region()
/external/igt-gpu-tools/tests/
Dperf.c69 #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12) macro
2867 PIPE_CONTROL_RENDER_TARGET_FLUSH | in emit_stall_timestamp_and_rpc()