Searched refs:PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (Results 1 – 16 of 16) sorted by relevance
200 [IRIS_DOMAIN_OTHER_READ] = (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in iris_emit_buffer_barrier_for()297 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in iris_flush_all_caches()318 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in iris_texture_barrier()328 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in iris_texture_barrier()345 bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in iris_memory_barrier()350 bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in iris_memory_barrier()
310 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15), enumerator333 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
320 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in tex_cache_flush_hack()
2146 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE : in iris_flush_bits_for_history()2151 flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; in iris_flush_bits_for_history()
468 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in flush_after_state_base_change()663 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in emit_pipeline_select()7116 if ((flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE) && in batch_mark_sync_for_pipe_control()7425 if (GEN_GEN >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { in iris_emit_raw_pipe_control()7529 (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE) ? "TC " : "", in iris_emit_raw_pipe_control()7585 flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; in iris_emit_raw_pipe_control()
56 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15), enumerator74 PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
350 if (GEN_GEN >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { in genX()501 flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; in genX()504 flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; in genX()
360 bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_memory_barrier()364 bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; in brw_memory_barrier()368 bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_memory_barrier()372 bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_memory_barrier()396 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_framebuffer_fetch_barrier()
368 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_emit_mi_flush()
106 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in setup_l3_config()
538 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_emit_select_pipeline()898 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_upload_state_base_address()
319 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in intel_texture_barrier()
525 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_blorp_copy_miptrees()535 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_blorp_copy_miptrees()
1027 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in flush_depth_and_render_caches()
443 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in gen9_apply_astc5x5_wa_flush()
71 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1 << 10) /* GM45+ only */ macro