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Searched refs:PKT3 (Results 1 – 25 of 39) sorted by relevance

12

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c59 si_pm4_cmd_add(pm4, PKT3(packet, 1 + num_ranges * 2, 0)); in si_build_load_reg()
75 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
80 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
85 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
89 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
98 si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in si_create_shadowing_ib_preamble()
113 si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 5, 0)); in si_create_shadowing_ib_preamble()
124 si_pm4_cmd_add(pm4, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_create_shadowing_ib_preamble()
127 si_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_create_shadowing_ib_preamble()
Dsi_build_pm4.h47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
85 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
95 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
110 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
131 radeon_emit(cs, PKT3(opcode, 1, 0)); in radeon_set_uconfig_reg_idx()
142 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); in radeon_set_context_reg_rmw()
Dsi_state_draw.c814 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); in si_emit_draw_packets()
850 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); in si_emit_draw_packets()
863 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); in si_emit_draw_packets()
867 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); in si_emit_draw_packets()
872 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT : PKT3_DRAW_INDIRECT, 3, in si_emit_draw_packets()
891 PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI : PKT3_DRAW_INDIRECT_MULTI, 8, in si_emit_draw_packets()
912 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); in si_emit_draw_packets()
957 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit)); in si_emit_draw_packets()
976 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit)); in si_emit_draw_packets()
995 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0)); in si_emit_surface_sync()
[all …]
Dsi_state_streamout.c240 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); in gfx10_emit_streamout_begin()
287 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_vgt_streamout()
290 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_flush_vgt_streamout()
326 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_begin()
338 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_begin()
370 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in si_emit_streamout_end()
Dsi_fence.c94 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cp_release_mem()
103 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, ctx->chip_class >= GFX9 ? 6 : 5, 0)); in si_cp_release_mem()
121 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); in si_cp_release_mem()
132 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); in si_cp_release_mem()
158 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_cp_wait_mem()
Dsi_cp_dma.c106 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_cp_dma()
116 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in si_emit_cp_dma()
130 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_emit_cp_dma()
588 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + size / 4, 0)); in si_cp_write_data()
610 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_cp_copy_data()
Dsi_compute_prim_discard.c1088 radeon_emit(gfx_cs, PKT3(PKT3_NOP, 0, 0)); in si_prepare_prim_discard_or_split_draw()
1188 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in si_dispatch_prim_discard_cs_and_draw()
1353 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + gds_size / 4, 0)); in si_dispatch_prim_discard_cs_and_draw()
1421 radeon_emit(gfx_cs, PKT3(PKT3_NOP, 0, 0)); in si_dispatch_prim_discard_cs_and_draw()
1434 radeon_emit(gfx_cs, PKT3(PKT3_REWIND, 0, 0)); in si_dispatch_prim_discard_cs_and_draw()
1445 radeon_emit(gfx_cs, PKT3(PKT3_DRAW_INDEX_2, 4, 0)); in si_dispatch_prim_discard_cs_and_draw()
1500 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) | PKT3_SHADER_TYPE_S(1)); in si_dispatch_prim_discard_cs_and_draw()
Dsi_pm4.c48 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate); in si_pm4_cmd_end()
Dsi_perfcounter.c840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_start()
856 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
858 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
882 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_read()
894 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in si_pc_emit_read()
/external/mesa3d/src/amd/vulkan/
Dradv_cs.h48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
63 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
80 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
91 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); in radeon_set_context_reg_rmw()
102 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
125 radeon_emit(cs, PKT3(opcode, 1, 0)); in radeon_set_sh_reg_idx()
135 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
145 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1)); in radeon_set_uconfig_reg_seq_perfctr()
169 radeon_emit(cs, PKT3(opcode, 1, 0)); in radeon_set_uconfig_reg_idx()
181 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radeon_set_privileged_config_reg()
Dsi_cmd_buffer.c190 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_graphics()
195 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0)); in si_emit_graphics()
488 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_graphics()
956 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cs_emit_write_event_eop()
962 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false)); in si_cs_emit_write_event_eop()
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
986 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
1003 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false)); in radv_cp_wait_mem()
1020 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | in si_emit_acquire_mem()
1030 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false)); in si_emit_acquire_mem()
[all …]
Dradv_sqtt.c205 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_start()
257 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_copy_thread_trace_info_regs()
283 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_stop()
287 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_stop()
299 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_emit_thread_trace_stop()
312 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_emit_thread_trace_stop()
325 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_emit_thread_trace_stop()
421 radeon_emit(device->thread_trace_start_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in radv_thread_trace_init_cs()
426 radeon_emit(device->thread_trace_start_cs[family], PKT3(PKT3_NOP, 0, 0)); in radv_thread_trace_init_cs()
461 radeon_emit(device->thread_trace_stop_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in radv_thread_trace_init_cs()
[all …]
Dradv_cmd_buffer.c570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); in radv_emit_write_data_packet()
595 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_cmd_buffer_trace_emit()
604 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cmd_buffer_after_draw()
926 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_sample_locations()
1256 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_batch_break_on_new_ps()
1719 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0)); in radv_update_zrange_precision()
1886 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating)); in radv_set_ds_clear_metadata()
1911 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating)); in radv_set_ds_clear_metadata()
1939 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating)); in radv_set_tc_compat_zrange_metadata()
2034 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0)); in radv_load_ds_clear_metadata()
[all …]
Dradv_query.c1653 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_begin_query()
1667 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_begin_query()
1682 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in emit_begin_query()
1702 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_begin_query()
1733 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_end_query()
1749 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_end_query()
1773 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in emit_end_query()
1790 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_end_query()
1911 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_CmdWriteTimestamp()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
174 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
188 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
204 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
Dr600_hw_context.c125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
238 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); in r600_flush_emit()
246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
250 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
443 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in r600_emit_pfp_sync_me()
470 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0)); in r600_emit_pfp_sync_me()
[all …]
Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_vgt_streamout()
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in r600_flush_vgt_streamout()
212 radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0)); in r600_emit_streamout_begin()
225 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_begin()
237 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_begin()
248 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_streamout_begin()
268 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); in r600_emit_streamout_end()
Devergreen_state.c1762 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ in evergreen_emit_image_state()
1765 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ in evergreen_emit_image_state()
1768 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */ in evergreen_emit_image_state()
1771 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */ in evergreen_emit_image_state()
1779 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/ in evergreen_emit_image_state()
1782 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); in evergreen_emit_image_state()
1786 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
1789 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); in evergreen_emit_image_state()
1793 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
1797 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); in evergreen_emit_image_state()
[all …]
Devergreen_hw_context.c129 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in evergreen_cp_dma_clear_buffer()
136 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in evergreen_cp_dma_clear_buffer()
Dr600_pipe.h881 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT… macro
904 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); in r600_store_config_reg_seq()
916 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; in r600_store_context_reg_seq()
928 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; in r600_store_ctl_const_seq()
936 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); in r600_store_loop_const_seq()
948 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; in eg_store_loop_const_seq()
996 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0)); in radeon_set_ctl_const_seq()
Dr600_state.c1389 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1402 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1415 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1439 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_framebuffer_state()
1462 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_framebuffer_state()
1476 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); in r600_emit_framebuffer_state()
1560 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_db_state()
1679 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); in r600_emit_vertex_buffers()
1691 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_vertex_buffers()
1723 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_constant_buffers()
[all …]
Dr600_state_common.c1688 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_setup_scratch_area_for_shader()
1706 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_setup_scratch_area_for_shader()
1724 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_setup_scratch_area_for_shader()
2293 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); in r600_draw_vbo()
2303 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0)); in r600_draw_vbo()
2308 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
2316 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); in r600_draw_vbo()
2324 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit)); in r600_draw_vbo()
2332 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit)); in r600_draw_vbo()
2337 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_draw_vbo()
[all …]
Dr600d_common.h40 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT… macro
Devergreen_compute.c702 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ in compute_setup_cbs()
705 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ in compute_setup_cbs()
784 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in compute_emit_cs()
861 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in compute_emit_cs()
1067 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); in evergreen_init_atom_start_compute_cs()
/external/mesa3d/src/amd/common/
Dsid.h244 #define PKT3(op, count, predicate) \ macro
248 #define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */

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