| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hikey_pm.c | 64 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey_pwr_domain_on_finish()
88 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_off()
104 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend()
107 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
114 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend()
119 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
124 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
139 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend_finish()
148 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend_finish()
153 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend_finish()
[all …]
|
| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | plat_pm.c | 158 PLAT_MAX_OFF_STATE; in rockchip_validate_power_state()
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state()
222 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in rockchip_pwr_domain_off()
226 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_off()
249 if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
255 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
261 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
264 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
286 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in rockchip_pwr_domain_on_finish()
298 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rockchip_pwr_domain_on_finish()
[all …]
|
| /external/arm-trusted-firmware/plat/renesas/common/ |
| D | plat_pm.c | 81 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_on_finish()
103 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_off()
117 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend()
125 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
133 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend()
143 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend_finish()
255 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
274 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| D | hikey960_pm.c | 85 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_on_finish()
164 PLAT_MAX_OFF_STATE; in hikey960_validate_power_state()
195 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_suspend()
198 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey960_pwr_domain_suspend()
216 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey960_pwr_domain_suspend()
272 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_suspend_finish()
294 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey960_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/imx/common/ |
| D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/hisilicon/poplar/ |
| D | plat_pm.c | 77 PLAT_MAX_OFF_STATE); in poplar_pwr_domain_on_finish()
122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
148 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in poplar_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | plat_psci.c | 196 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
212 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
213 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
| D | plat_psci.c | 173 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/ti/k3/common/ |
| D | k3_psci.c | 91 assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in k3_pwr_domain_off()
107 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in k3_pwr_domain_off()
137 if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in k3_pwr_domain_off()
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/ |
| D | plat_psci_handlers.c | 43 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; in tegra_soc_get_target_pwr_state()
81 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in tegra_soc_validate_power_state()
|
| /external/arm-trusted-firmware/plat/intel/soc/common/ |
| D | socfpga_psci.c | 192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/ti/k3/board/lite/include/ |
| D | board_def.h | 27 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/ti/k3/board/generic/include/ |
| D | board_def.h | 25 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/lib/psci/ |
| D | psci_setup.c | 54 PLAT_MAX_OFF_STATE; in psci_init_pwr_domain_node()
75 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; in psci_init_pwr_domain_node()
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/ |
| D | plat_psci_handlers.c | 184 if (target != PLAT_MAX_OFF_STATE) { in tegra_last_cpu_in_cluster()
224 if (target == PLAT_MAX_OFF_STATE) { in tegra_get_afflvl1_pwr_state()
398 if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { in tegra_soc_pwr_domain_on_finish()
|
| /external/arm-trusted-firmware/plat/allwinner/common/ |
| D | sunxi_pm.c | 198 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_validate_power_state()
222 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey/include/ |
| D | platform_def.h | 40 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/ |
| D | plat_psci_handlers.c | 82 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in tegra_soc_validate_power_state()
208 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || in tegra_soc_pwr_domain_suspend()
210 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || in tegra_soc_pwr_domain_suspend()
|
| /external/arm-trusted-firmware/plat/amlogic/g12a/include/ |
| D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/amlogic/gxl/include/ |
| D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/amlogic/gxbb/include/ |
| D | platform_def.h | 35 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/amlogic/axg/include/ |
| D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/allwinner/common/include/ |
| D | platform_def.h | 45 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/imx/imx8qx/include/ |
| D | platform_def.h | 27 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /external/arm-trusted-firmware/plat/rockchip/rk3288/include/ |
| D | platform_def.h | 62 #define PLAT_MAX_OFF_STATE U(2) macro
|