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Searched refs:PLL_MODE (Results 1 – 2 of 2) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
/external/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
Dmisc_regs.h21 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) macro