/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/ |
D | pmu.c | 33 regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b); in rk3368_flash_l2_b() 36 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) in rk3368_flash_l2_b() 41 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); in rk3368_flash_l2_b() 44 regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b); in rk3368_flash_l2_b() 146 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); in rk3368_pmu_bus_idle() 152 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); in rk3368_pmu_bus_idle() 154 while ((mmio_read_32(PMU_BASE + in rk3368_pmu_bus_idle() 159 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), in rk3368_pmu_bus_idle() 168 regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b); in pmu_scu_b_pwrup() 176 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn() [all …]
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/external/arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/ |
D | pmu.c | 126 return mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd) ? in pmu_power_domain_st() 138 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, in pmu_power_domain_ctr() 159 return !!((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus)) && in pmu_bus_idle_st() 160 (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus + 16))); in pmu_bus_idle_st() 167 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_REQ, in pmu_bus_idle_req() 178 __func__, mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), bus); in pmu_bus_idle_req() 325 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in pmu_power_domains_suspend() 396 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on() 399 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on() 419 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on() [all …]
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/ |
D | suspend.c | 25 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main() 27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main() 44 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main() 46 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main() 53 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main() 55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
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D | dram.c | 21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in idle_port() 23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in idle_port() 31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port() 33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in deidle_port()
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/ |
D | pmu.c | 83 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); in pmu_bus_idle_req() 86 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; in pmu_bus_idle_req() 87 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; in pmu_bus_idle_req() 97 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), in pmu_bus_idle_req() 100 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), in pmu_bus_idle_req() 334 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in pmu_power_domains_suspend() 426 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b() 433 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & in rk3399_flush_l2_b() 441 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b() 448 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn() [all …]
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D | plat_pmu_macros.S | 89 mov x5, PMU_BASE 116 mov x5, PMU_BASE
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/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/ |
D | pmu.c | 103 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); in rk3288_pmu_bus_idle() 109 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); in rk3288_pmu_bus_idle() 111 while ((mmio_read_32(PMU_BASE + in rk3288_pmu_bus_idle() 116 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), in rk3288_pmu_bus_idle() 170 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode() 180 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 32 * 30); in pmu_set_sleep_mode() 183 mmio_write_32(PMU_BASE + PMU_OSC_CNT, in pmu_set_sleep_mode() 193 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode() 198 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 24000 * 30); in pmu_set_sleep_mode() 201 mmio_write_32(PMU_BASE + PMU_OSC_CNT, 0); in pmu_set_sleep_mode() [all …]
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/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/ |
D | pmu.c | 40 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id); in get_cpus_pwr_domain_cfg_info() 41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info() 63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on() 68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on() 79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on() 98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off() 106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off() 179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish() 188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume() 509 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in ddr_suspend() [all …]
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/external/arm-trusted-firmware/plat/rockchip/common/drivers/pmu/ |
D | pmu_com.h | 11 #define CHECK_CPU_WFIE_BASE (PMU_BASE + PMU_CORE_PWR_ST) 40 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); in pmu_power_domain_st() 56 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); in pmu_power_domain_ctr() 62 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); in pmu_power_domain_ctr()
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/external/arm-trusted-firmware/plat/rockchip/rk3368/ |
D | rk3368_def.h | 31 #define PMU_BASE 0xff730000 macro
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/external/arm-trusted-firmware/plat/rockchip/rk3288/ |
D | rk3288_def.h | 54 #define PMU_BASE 0xff730000 macro
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/external/arm-trusted-firmware/plat/rockchip/rk3328/ |
D | rk3328_def.h | 27 #define PMU_BASE 0xff140000 macro
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/external/arm-trusted-firmware/plat/rockchip/px30/ |
D | px30_def.h | 21 #define PMU_BASE 0xff000000 macro
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/external/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/ |
D | addressmap_shared.h | 26 #define PMU_BASE (MMIO_BASE + 0x07310000) macro
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
D | suspend.c | 591 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); in pctl_start() 593 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); in pctl_start() 684 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE); in pmusram_enable_watchdog()
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D | dfs.c | 1756 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & in exit_low_power() 1758 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); in exit_low_power() 1759 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) in exit_low_power() 1792 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); in resume_low_power()
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/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/ |
D | soc.c | 28 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/ |
D | soc.c | 35 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/ |
D | soc.c | 31 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ |
D | ddr_rk3368.c | 428 p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM; in ddr_reg_save()
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