1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RK3368_DEF_H 8 #define RK3368_DEF_H 9 10 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 11 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 12 13 #define CCI400_BASE 0xffb90000 14 #define CCI400_SIZE 0x10000 15 16 #define GIC400_BASE 0xffb70000 17 #define GIC400_SIZE 0x10000 18 19 #define STIME_BASE 0xff830000 20 #define STIME_SIZE 0x10000 21 22 #define CRU_BASE 0xff760000 23 #define CRU_SIZE 0x10000 24 25 #define GRF_BASE 0xff770000 26 #define GRF_SIZE 0x10000 27 28 #define SGRF_BASE 0xff740000 29 #define SGRF_SIZE 0x10000 30 31 #define PMU_BASE 0xff730000 32 #define PMU_GRF_BASE 0xff738000 33 #define PMU_SIZE 0x10000 34 35 #define RK_INTMEM_BASE 0xff8c0000 36 #define RK_INTMEM_SIZE 0x10000 37 38 #define UART0_BASE 0xff180000 39 #define UART0_SIZE 0x10000 40 41 #define UART1_BASE 0xff190000 42 #define UART1_SIZE 0x10000 43 44 #define UART2_BASE 0xff690000 45 #define UART2_SIZE 0x10000 46 47 #define UART3_BASE 0xff1b0000 48 #define UART3_SIZE 0x10000 49 50 #define UART4_BASE 0xff1c0000 51 #define UART4_SIZE 0x10000 52 53 #define CRU_BASE 0xff760000 54 55 #define PMUSRAM_BASE 0xff720000 56 #define PMUSRAM_SIZE 0x10000 57 #define PMUSRAM_RSIZE 0x1000 58 59 #define DDR_PCTL_BASE 0xff610000 60 #define DDR_PCTL_SIZE 0x10000 61 62 #define DDR_PHY_BASE 0xff620000 63 #define DDR_PHY_SIZE 0x10000 64 65 #define SERVICE_BUS_BASE 0xffac0000 66 #define SERVICE_BUS_SISE 0x50000 67 68 #define COLD_BOOT_BASE 0xffff0000 69 /************************************************************************** 70 * UART related constants 71 **************************************************************************/ 72 #define RK3368_BAUDRATE 115200 73 #define RK3368_UART_CLOCK 24000000 74 75 /****************************************************************************** 76 * System counter frequency related constants 77 ******************************************************************************/ 78 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 79 80 /****************************************************************************** 81 * GIC-400 & interrupt handling related constants 82 ******************************************************************************/ 83 84 /* Base rk_platform compatible GIC memory map */ 85 #define RK3368_GICD_BASE (GIC400_BASE + 0x1000) 86 #define RK3368_GICC_BASE (GIC400_BASE + 0x2000) 87 #define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */ 88 89 /***************************************************************************** 90 * CCI-400 related constants 91 ******************************************************************************/ 92 #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3 93 #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4 94 95 /****************************************************************************** 96 * sgi, ppi 97 ******************************************************************************/ 98 #define RK_IRQ_SEC_PHY_TIMER 29 99 100 #define RK_IRQ_SEC_SGI_0 8 101 #define RK_IRQ_SEC_SGI_1 9 102 #define RK_IRQ_SEC_SGI_2 10 103 #define RK_IRQ_SEC_SGI_3 11 104 #define RK_IRQ_SEC_SGI_4 12 105 #define RK_IRQ_SEC_SGI_5 13 106 #define RK_IRQ_SEC_SGI_6 14 107 #define RK_IRQ_SEC_SGI_7 15 108 109 /* 110 * Define a list of Group 0 interrupts. 111 */ 112 #define PLAT_RK_GICV2_G0_IRQS \ 113 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) 115 116 #endif /* RK3368_DEF_H */ 117