1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #ifndef PM_API_IOCTL_H 12 #define PM_API_IOCTL_H 13 14 #include "pm_common.h" 15 16 //ioctl id 17 enum { 18 IOCTL_GET_RPU_OPER_MODE, 19 IOCTL_SET_RPU_OPER_MODE, 20 IOCTL_RPU_BOOT_ADDR_CONFIG, 21 IOCTL_TCM_COMB_CONFIG, 22 IOCTL_SET_TAPDELAY_BYPASS, 23 IOCTL_SET_SGMII_MODE, 24 IOCTL_SD_DLL_RESET, 25 IOCTL_SET_SD_TAPDELAY, 26 /* Ioctl for clock driver */ 27 IOCTL_SET_PLL_FRAC_MODE, 28 IOCTL_GET_PLL_FRAC_MODE, 29 IOCTL_SET_PLL_FRAC_DATA, 30 IOCTL_GET_PLL_FRAC_DATA, 31 IOCTL_WRITE_GGS, 32 IOCTL_READ_GGS, 33 IOCTL_WRITE_PGGS, 34 IOCTL_READ_PGGS, 35 /* IOCTL for ULPI reset */ 36 IOCTL_ULPI_RESET, 37 /* Set healthy bit value */ 38 IOCTL_SET_BOOT_HEALTH_STATUS, 39 IOCTL_AFI, 40 }; 41 42 //RPU operation mode 43 #define PM_RPU_MODE_LOCKSTEP 0U 44 #define PM_RPU_MODE_SPLIT 1U 45 46 //RPU boot mem 47 #define PM_RPU_BOOTMEM_LOVEC 0U 48 #define PM_RPU_BOOTMEM_HIVEC 1U 49 50 //RPU tcm mpde 51 #define PM_RPU_TCM_SPLIT 0U 52 #define PM_RPU_TCM_COMB 1U 53 54 //tap delay signal type 55 #define PM_TAPDELAY_NAND_DQS_IN 0U 56 #define PM_TAPDELAY_NAND_DQS_OUT 1U 57 #define PM_TAPDELAY_QSPI 2U 58 #define PM_TAPDELAY_MAX 3U 59 60 //tap delay bypass 61 #define PM_TAPDELAY_BYPASS_DISABLE 0U 62 #define PM_TAPDELAY_BYPASS_ENABLE 1U 63 64 //sgmii mode 65 #define PM_SGMII_DISABLE 0U 66 #define PM_SGMII_ENABLE 1U 67 68 enum tap_delay_type { 69 PM_TAPDELAY_INPUT, 70 PM_TAPDELAY_OUTPUT, 71 }; 72 73 //dll reset type 74 #define PM_DLL_RESET_ASSERT 0U 75 #define PM_DLL_RESET_RELEASE 1U 76 #define PM_DLL_RESET_PULSE 2U 77 78 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 79 unsigned int ioctl_id, 80 unsigned int arg1, 81 unsigned int arg2, 82 unsigned int *value); 83 #endif /* PM_API_IOCTL_H */ 84