| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGAddressAnalysis.cpp | 183 } else if (N->getAddressingMode() == ISD::PRE_DEC) { in matchLSNode()
216 if (LSBase->getAddressingMode() == ISD::PRE_DEC || in matchLSNode()
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| D | SelectionDAGDumper.cpp | 458 case ISD::PRE_DEC: return "<pre-dec>"; in getIndexedModeName()
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| D | DAGCombiner.cpp | 13785 if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, in CombineToPreIndexedLoadStore()
13966 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
13967 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
14225 bool IsSub = (LD->getAddressingMode() == ISD::PRE_DEC || in ForwardStoreValueToDirectLoad()
20822 : (LSN->getAddressingMode() == ISD::PRE_DEC) in isAlias()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGAddressAnalysis.cpp | 194 } else if (N->getAddressingMode() == ISD::PRE_DEC) { in matchLSNode()
227 if (LSBase->getAddressingMode() == ISD::PRE_DEC || in matchLSNode()
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| D | SelectionDAGDumper.cpp | 485 case ISD::PRE_DEC: return "<pre-dec>"; in getIndexedModeName()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 810 PRE_DEC, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 988 PRE_DEC, enumerator
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| D | BasicTTIImpl.h | 181 return ISD::PRE_DEC; in getISDIndexedMode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 129 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad()
135 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad()
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| D | AVRISelLowering.cpp | 118 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
122 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
817 AM = ISD::PRE_DEC; in getPreIndexedAddressParts()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 129 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad()
135 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad()
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| D | AVRISelLowering.cpp | 119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
816 AM = ISD::PRE_DEC; in getPreIndexedAddressParts()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1212 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
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| D | BasicTTIImpl.h | 178 return ISD::PRE_DEC; in getISDIndexedMode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 366 case ISD::PRE_DEC: return "<pre-dec>"; in getIndexedModeName()
|
| D | DAGCombiner.cpp | 9671 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) in CombineToPreIndexedLoadStore()
9679 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) in CombineToPreIndexedLoadStore()
9852 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
9853 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 876 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
886 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1529 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1636 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1700 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1716 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1576 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1683 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1747 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1763 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 1136 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1147 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 1143 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1154 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1479 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1555 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1047 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1192 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1272 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad()
|