| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-intrinsics-pred-testing.ll | 8 ; PTEST
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 365 PTEST, enumerator
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| D | X86SchedHaswell.td | 1554 // PTEST.
1561 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>;
1569 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>;
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| D | X86InstrFragmentsSIMD.td | 270 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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| D | X86ISelLowering.cpp | 14571 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, in LowerVectorAllZeroTest()
18018 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; in LowerINTRINSIC_WO_CHAIN()
22220 case X86ISD::PTEST: return "X86ISD::PTEST"; in getTargetNodeName()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 215 PTEST, enumerator
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| D | AArch64SVEInstrInfo.td | 77 def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
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| D | AArch64ISelLowering.cpp | 1384 case AArch64ISD::PTEST: return "AArch64ISD::PTEST"; in getTargetNodeName()
10983 SDValue Test = DAG.getNode(AArch64ISD::PTEST, DL, MVT::Other, Pg, Op); in getPTest()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 305 PTEST, enumerator
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| D | AArch64SVEInstrInfo.td | 244 def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
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| D | AArch64ISelLowering.cpp | 1875 MAKE_CASE(AArch64ISD::PTEST) in getTargetNodeName()
13134 SDValue Test = DAG.getNode(AArch64ISD::PTEST, DL, MVT::Other, Pg, Op); in getPTest()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 421 PTEST, enumerator
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| D | X86.td | 425 "Prefer AVX512 mask registers over PTEST/MOVMSK">;
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| D | X86InstrFragmentsSIMD.td | 292 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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| D | X86ISelLowering.cpp | 21838 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, V, V); in LowerVectorAllZero()
25381 unsigned TestOpc = X86ISD::PTEST; in LowerINTRINSIC_WO_CHAIN()
30892 NODE_NAME_CASE(PTEST) in getTargetNodeName()
41398 if (EFLAGS.getOpcode() != X86ISD::PTEST && in combinePTESTCC()
41590 return DAG.getNode(X86ISD::PTEST, SDLoc(EFLAGS), MVT::i32, V, V); in combineSetCCMOVMSK()
47259 SDValue PT = DAG.getNode(X86ISD::PTEST, DL, MVT::i32, BCCmp, BCCmp); in combineVectorSizedSetCCEquality()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 357 PTEST, enumerator
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| D | X86.td | 391 "Prefer AVX512 mask registers over PTEST/MOVMSK">;
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| D | X86InstrFragmentsSIMD.td | 283 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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| D | X86ISelLowering.cpp | 20672 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, VecIns.back(), VecIns.back()); in LowerVectorAllZeroTest()
21832 if (SDValue PTEST = LowerVectorAllZeroTest(Op0, CC, Subtarget, DAG, X86CC)) in emitFlagsForSetcc() local
21833 return PTEST; in emitFlagsForSetcc()
24242 unsigned TestOpc = X86ISD::PTEST; in LowerINTRINSIC_WO_CHAIN()
29749 case X86ISD::PTEST: return "X86ISD::PTEST"; in getTargetNodeName()
43840 SDValue PT = DAG.getNode(X86ISD::PTEST, DL, MVT::i32, BCCmp, BCCmp); in combineVectorSizedSetCCEquality()
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | setcc-wide-types.ll | 9 ; Equality checks of 128/256-bit values can use PMOVMSK or PTEST to avoid scalarization.
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenFastISel.inc | 5585 // FastEmit functions for AArch64ISD::PTEST.
9796 …case AArch64ISD::PTEST: return fastEmit_AArch64ISD_PTEST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsK…
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 13228 // FastEmit functions for X86ISD::PTEST.
15197 case X86ISD::PTEST: return fastEmit_X86ISD_PTEST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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| D | X86GenSubtargetInfo.inc | 240 …{ "prefer-mask-registers", "Prefer AVX512 mask registers over PTEST/MOVMSK", X86::FeaturePreferMas…
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