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/external/llvm-project/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll34 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
35 ; MIPS32R6: lw $2, 0($[[PTR]])
49 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
50 ; MIPS64R6: lw $2, 0($[[PTR]])
66 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
67 ; MIPS32R6: sw $4, 0($[[PTR]])
81 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
82 ; MIPS64R6: sw $4, 0($[[PTR]])
102 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sll)(
103 ; MIPS32R6-DAG: lw $2, 0($[[PTR]])
[all …]
/external/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll34 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
35 ; MIPS32R6: lw $2, 0($[[PTR]])
43 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
44 ; MIPS64R6: lw $2, 0($[[PTR]])
60 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
61 ; MIPS32R6: sw $4, 0($[[PTR]])
69 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
70 ; MIPS64R6: sw $4, 0($[[PTR]])
90 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sll)(
91 ; MIPS32R6-DAG: lw $2, 0($[[PTR]])
[all …]
/external/python/cffi/c/libffi_msvc/
Dwin64.asm20 mov QWORD PTR [rsp+8], rcx
23 movlpd QWORD PTR [rsp+8], xmm0
28 mov QWORD PTR [rsp+16], rdx
31 movlpd QWORD PTR [rsp+16], xmm1
36 mov QWORD PTR [rsp+24], r8
39 movlpd QWORD PTR [rsp+24], xmm2
44 mov QWORD PTR [rsp+32], r9
47 movlpd QWORD PTR [rsp+32], xmm3
77 mov QWORD PTR [rsp+32], r9
78 mov QWORD PTR [rsp+24], r8
[all …]
/external/python/cpython2/Modules/_ctypes/libffi_msvc/
Dwin64.asm20 mov QWORD PTR [rsp+8], rcx
23 movlpd QWORD PTR [rsp+8], xmm0
28 mov QWORD PTR [rsp+16], rdx
31 movlpd QWORD PTR [rsp+16], xmm1
36 mov QWORD PTR [rsp+24], r8
39 movlpd QWORD PTR [rsp+24], xmm2
44 mov QWORD PTR [rsp+32], r9
47 movlpd QWORD PTR [rsp+32], xmm3
77 mov QWORD PTR [rsp+32], r9
78 mov QWORD PTR [rsp+24], r8
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/x86/
Dwin64.S39 mov QWORD PTR [rsp+8], rcx
42 movlpd QWORD PTR [rsp+8], xmm0
47 mov QWORD PTR [rsp+16], rdx
50 movlpd QWORD PTR [rsp+16], xmm1
55 mov QWORD PTR [rsp+24], r8
58 movlpd QWORD PTR [rsp+24], xmm2
63 mov QWORD PTR [rsp+32], r9
66 movlpd QWORD PTR [rsp+32], xmm3
85 mov QWORD PTR [rsp+32], r9
86 mov QWORD PTR [rsp+24], r8
[all …]
/external/llvm-project/openmp/runtime/src/
Dz_Windows_NT-586_asm.asm88 mov eax, DWORD PTR _mode$[ebp]
89 mov ecx, DWORD PTR _mode2$[ebp]
92 mov edi, DWORD PTR _p$[ebp]
93 mov DWORD PTR _eax$[ edi ], eax
94 mov DWORD PTR _ebx$[ edi ], ebx
95 mov DWORD PTR _ecx$[ edi ], ecx
96 mov DWORD PTR _edx$[ edi ], edx
122 mov eax, DWORD PTR _d$[esp]
123 mov ecx, DWORD PTR _p$[esp]
124 lock xadd DWORD PTR [ecx], eax
[all …]
/external/llvm-project/llvm/test/Transforms/PhaseOrdering/
Dinlining-alignment-assumptions.ll21 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR:%.*]], align 8
22 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
23 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
24 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
25 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
26 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
27 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 2, i64* [[PTR]], align 4
30 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4
31 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR]], align 8
32 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
[all …]
/external/llvm-project/clang/include/clang/AST/
DEvaluatedExprVisitor.h35 #define PTR(CLASS) typename Ptr<CLASS>::type macro
41 void VisitDeclRefExpr(PTR(DeclRefExpr) E) { } in VisitDeclRefExpr()
42 void VisitOffsetOfExpr(PTR(OffsetOfExpr) E) { } in VisitOffsetOfExpr()
43 void VisitUnaryExprOrTypeTraitExpr(PTR(UnaryExprOrTypeTraitExpr) E) { } in VisitUnaryExprOrTypeTraitExpr()
44 void VisitExpressionTraitExpr(PTR(ExpressionTraitExpr) E) { } in VisitExpressionTraitExpr()
45 void VisitBlockExpr(PTR(BlockExpr) E) { } in VisitBlockExpr()
46 void VisitCXXUuidofExpr(PTR(CXXUuidofExpr) E) { } in VisitCXXUuidofExpr()
47 void VisitCXXNoexceptExpr(PTR(CXXNoexceptExpr) E) { } in VisitCXXNoexceptExpr()
49 void VisitMemberExpr(PTR(MemberExpr) E) { in VisitMemberExpr()
54 void VisitChooseExpr(PTR(ChooseExpr) E) { in VisitChooseExpr()
[all …]
/external/clang/include/clang/AST/
DEvaluatedExprVisitor.h35 #define PTR(CLASS) typename Ptr<CLASS>::type macro
41 void VisitDeclRefExpr(PTR(DeclRefExpr) E) { } in VisitDeclRefExpr()
42 void VisitOffsetOfExpr(PTR(OffsetOfExpr) E) { } in VisitOffsetOfExpr()
43 void VisitUnaryExprOrTypeTraitExpr(PTR(UnaryExprOrTypeTraitExpr) E) { } in VisitUnaryExprOrTypeTraitExpr()
44 void VisitExpressionTraitExpr(PTR(ExpressionTraitExpr) E) { } in VisitExpressionTraitExpr()
45 void VisitBlockExpr(PTR(BlockExpr) E) { } in VisitBlockExpr()
46 void VisitCXXUuidofExpr(PTR(CXXUuidofExpr) E) { } in VisitCXXUuidofExpr()
47 void VisitCXXNoexceptExpr(PTR(CXXNoexceptExpr) E) { } in VisitCXXNoexceptExpr()
49 void VisitMemberExpr(PTR(MemberExpr) E) { in VisitMemberExpr()
54 void VisitChooseExpr(PTR(ChooseExpr) E) { in VisitChooseExpr()
[all …]
DStmtVisitor.h36 #define PTR(CLASS) typename Ptr<CLASS>::type macro
38 return static_cast<ImplClass*>(this)->Visit ## NAME(static_cast<PTR(CLASS)>(S))
40 RetTy Visit(PTR(Stmt) S) { in Visit()
45 if (PTR(BinaryOperator) BinOp = dyn_cast<BinaryOperator>(S)) { in Visit()
82 } else if (PTR(UnaryOperator) UnOp = dyn_cast<UnaryOperator>(S)) { in Visit()
114 RetTy Visit ## CLASS(PTR(CLASS) S) { DISPATCH(PARENT, PARENT); }
120 RetTy VisitBin ## NAME(PTR(BinaryOperator) S) { \
140 RetTy VisitBin ## NAME(PTR(CompoundAssignOperator) S) { \ in BINOP_FALLBACK()
152 RetTy VisitUnary ## NAME(PTR(UnaryOperator) S) { \
166 RetTy VisitStmt(PTR(Stmt) Node) { return RetTy(); }
[all …]
/external/libvpx/libvpx/vp8/common/x86/
Dsubpixel_ssse3.asm49 movsxd rdx, DWORD PTR arg(5) ;table index
59 cmp esi, DWORD PTR [rax]
62 movdqa xmm4, XMMWORD PTR [rax] ;k0_k5
63 movdqa xmm5, XMMWORD PTR [rax+256] ;k2_k4
64 movdqa xmm6, XMMWORD PTR [rax+128] ;k1_k3
75 movq xmm0, MMWORD PTR [rsi - 2] ; -2 -1 0 1 2 3 4 5
77 movq xmm2, MMWORD PTR [rsi + 3] ; 3 4 5 6 7 8 9 10
118 movdqa xmm5, XMMWORD PTR [rax+256] ;k2_k4
119 movdqa xmm6, XMMWORD PTR [rax+128] ;k1_k3
121 movdqa xmm3, XMMWORD PTR [GLOBAL(shuf2bfrom1)]
[all …]
/external/libvpx/libvpx/vp8/encoder/x86/
Dcopy_sse2.asm40 movdqu xmm0, XMMWORD PTR [rsi]
41 movdqu xmm1, XMMWORD PTR [rsi + 16]
42 movdqu xmm2, XMMWORD PTR [rsi + rax]
43 movdqu xmm3, XMMWORD PTR [rsi + rax + 16]
47 movdqu xmm4, XMMWORD PTR [rsi]
48 movdqu xmm5, XMMWORD PTR [rsi + 16]
49 movdqu xmm6, XMMWORD PTR [rsi + rax]
50 movdqu xmm7, XMMWORD PTR [rsi + rax + 16]
54 movdqa XMMWORD PTR [rdi], xmm0
55 movdqa XMMWORD PTR [rdi + 16], xmm1
[all …]
Dcopy_sse3.asm102 movdqu xmm0, XMMWORD PTR [src_ptr]
103 movdqu xmm1, XMMWORD PTR [src_ptr + 16]
104 movdqu xmm2, XMMWORD PTR [src_ptr + src_stride]
105 movdqu xmm3, XMMWORD PTR [src_ptr + src_stride + 16]
106 movdqu xmm4, XMMWORD PTR [end_ptr]
107 movdqu xmm5, XMMWORD PTR [end_ptr + 16]
108 movdqu xmm6, XMMWORD PTR [end_ptr + src_stride]
109 movdqu xmm7, XMMWORD PTR [end_ptr + src_stride + 16]
115 movdqa XMMWORD PTR [ref_ptr], xmm0
116 movdqa XMMWORD PTR [ref_ptr + 16], xmm1
[all …]
Ddct_sse2.asm71 movq xmm0, MMWORD PTR[input ] ;03 02 01 00
72 movq xmm2, MMWORD PTR[input+ pitch] ;13 12 11 10
74 movq xmm1, MMWORD PTR[input ] ;23 22 21 20
75 movq xmm3, MMWORD PTR[input+ pitch] ;33 32 31 30
96 pmaddwd xmm0, XMMWORD PTR[GLOBAL(_mult_add)] ;a1 + b1
97 pmaddwd xmm1, XMMWORD PTR[GLOBAL(_mult_sub)] ;a1 - b1
99 pmaddwd xmm3, XMMWORD PTR[GLOBAL(_5352_2217)] ;c1*2217 + d1*5352
100 pmaddwd xmm4, XMMWORD PTR[GLOBAL(_2217_neg5352)];d1*2217 - c1*5352
102 paddd xmm3, XMMWORD PTR[GLOBAL(_14500)]
103 paddd xmm4, XMMWORD PTR[GLOBAL(_7500)]
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dsad_sse3.asm84 movdqa xmm0, XMMWORD PTR [%2]
85 lddqu xmm5, XMMWORD PTR [%3]
86 lddqu xmm6, XMMWORD PTR [%3+1]
87 lddqu xmm7, XMMWORD PTR [%3+2]
93 movdqa xmm0, XMMWORD PTR [%2]
94 lddqu xmm1, XMMWORD PTR [%3]
95 lddqu xmm2, XMMWORD PTR [%3+1]
96 lddqu xmm3, XMMWORD PTR [%3+2]
106 movdqa xmm0, XMMWORD PTR [%2+%4]
107 lddqu xmm1, XMMWORD PTR [%3+%5]
[all …]
Dsad_sse4.asm16 movdqa xmm0, XMMWORD PTR [rsi]
17 movq xmm1, MMWORD PTR [rdi]
18 movq xmm3, MMWORD PTR [rdi+8]
19 movq xmm2, MMWORD PTR [rdi+16]
37 movdqa xmm0, XMMWORD PTR [rsi]
38 movq xmm5, MMWORD PTR [rdi]
39 movq xmm3, MMWORD PTR [rdi+8]
40 movq xmm2, MMWORD PTR [rdi+16]
60 movdqa xmm0, XMMWORD PTR [rsi + rax]
61 movq xmm5, MMWORD PTR [rdi+ rdx]
[all …]
Dhighbd_variance_impl_sse2.asm39 movsxd rax, DWORD PTR arg(1) ;[src_stride]
40 movsxd rdx, DWORD PTR arg(3) ;[ref_stride]
72 movdqu xmm1, XMMWORD PTR [rsi]
73 movdqu xmm2, XMMWORD PTR [rdi]
89 movdqu xmm3, XMMWORD PTR [rsi+16]
92 movdqu xmm2, XMMWORD PTR [rdi+16]
96 movdqu xmm1, XMMWORD PTR [rsi+rax]
99 movdqu xmm2, XMMWORD PTR [rdi+rdx]
103 movdqu xmm3, XMMWORD PTR [rsi+rax+16]
106 movdqu xmm2, XMMWORD PTR [rdi+rdx+16]
[all …]
/external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/
Dstack-poisoning-and-lifetime-be.ll29 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*
30 ; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1
34 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]*
35 ; ENTRY-NEXT: store [[TYPE]] 212499257711850226, [[TYPE]]* [[PTR]], align 1
39 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]*
40 ; ENTRY-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1
44 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]*
45 ; ENTRY-NEXT: store [[TYPE]] -1008799775530680320, [[TYPE]]* [[PTR]], align 1
49 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*
50 ; ENTRY-NEXT: store [[TYPE]] -202116109, [[TYPE]]* [[PTR]], align 1
[all …]
Dstack-poisoning-and-lifetime.ll29 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*
30 ; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1
34 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]*
35 ; ENTRY-NEXT: store [[TYPE]] -940422246894996990, [[TYPE]]* [[PTR]], align 1
39 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]*
40 ; ENTRY-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1
44 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]*
45 ; ENTRY-NEXT: store [[TYPE]] 1043442499826, [[TYPE]]* [[PTR]], align 1
49 ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*
50 ; ENTRY-NEXT: store [[TYPE]] -202116109, [[TYPE]]* [[PTR]], align 1
[all …]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/
Dunprofitable-pr.ll13 ; CHECK-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 4
14 ; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[PTR]] to i64
18 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
19 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
22 ; CHECK-NEXT: [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64
26 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
27 ; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8
58 ; CHECK-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 4
59 ; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[PTR]] to i64
63 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.ds.consume.ll7 ; GCN: s_load_dword [[PTR:s[0-9]+]]
8 ; GCN: s_mov_b32 m0, [[PTR]]
19 ; GCN: s_load_dword [[PTR:s[0-9]+]]
20 ; GCN: s_mov_b32 m0, [[PTR]]
32 ; GCN: s_load_dword [[PTR:s[0-9]+]]
34 ; SI: s_add_i32 [[PTR]], [[PTR]], 16
35 ; SI: s_mov_b32 m0, [[PTR]]
38 ; CIPLUS: s_mov_b32 m0, [[PTR]]
52 ; GCN: s_load_dword [[PTR:s[0-9]+]]
54 ; SI: s_bitset1_b32 [[PTR]], 16
[all …]
Dllvm.amdgcn.ds.append.ll7 ; GCN: s_load_dword [[PTR:s[0-9]+]]
8 ; GCN: s_mov_b32 m0, [[PTR]]
19 ; GCN: s_load_dword [[PTR:s[0-9]+]]
20 ; GCN: s_mov_b32 m0, [[PTR]]
32 ; GCN: s_load_dword [[PTR:s[0-9]+]]
34 ; SI: s_add_i32 [[PTR]], [[PTR]], 16
35 ; SI: s_mov_b32 m0, [[PTR]]
38 ; CIPLUS: s_mov_b32 m0, [[PTR]]
52 ; GCN: s_load_dword [[PTR:s[0-9]+]]
54 ; SI-SDAG: s_bitset1_b32 [[PTR]], 16
[all …]
/external/llvm/test/MC/X86/
Dintel-syntax.s11 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP + 4], 258
15 mov QWORD PTR [RSP - 16], 123
17 mov BYTE PTR [RSP - 17], 97
19 mov EAX, DWORD PTR [RSP - 4]
21 mov RAX, QWORD PTR [RSP]
23 mov DWORD PTR [RSP - 4], -4
25 mov RCX, QWORD PTR [0]
27 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
29 mov BYTE PTR [RDX + RCX], DIL
[all …]
/external/llvm-project/clang/test/CodeGenOpenCLCXX/
Daddress-space-deduction.cl1 …le spir-unknown-unknown -cl-std=clc++ -O0 -emit-llvm -o - | FileCheck %s -check-prefixes=COMMON,PTR
5 #define PTR &
8 #define PTR *
14 //PTR: @glob_p = addrspace(1) global i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @glob to i3…
16 int PTR glob_p = ADR(glob);
19 //PTR: @_ZZ3fooiPU3AS4iE8loc_st_p = internal addrspace(1) global i32 addrspace(4)* addrspacecast (i…
25 int foo(int par, int PTR par_p){
32 int PTR loc_p = ADR(loc);
34 const __private int PTR loc_p_const = ADR(loc);
38 static int PTR loc_st_p = ADR(loc_st);
[all …]
/external/libaom/libaom/aom_dsp/x86/
Dhighbd_variance_impl_sse2.asm42 movsxd rax, DWORD PTR arg(1) ;[source_stride]
43 movsxd rdx, DWORD PTR arg(3) ;[recon_stride]
75 movdqu xmm1, XMMWORD PTR [rsi]
76 movdqu xmm2, XMMWORD PTR [rdi]
92 movdqu xmm3, XMMWORD PTR [rsi+16]
95 movdqu xmm2, XMMWORD PTR [rdi+16]
99 movdqu xmm1, XMMWORD PTR [rsi+rax]
102 movdqu xmm2, XMMWORD PTR [rdi+rdx]
106 movdqu xmm3, XMMWORD PTR [rsi+rax+16]
109 movdqu xmm2, XMMWORD PTR [rdi+rdx+16]
[all …]

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