1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MTSPMC_PRIVATE_H 8 #define MTSPMC_PRIVATE_H 9 10 /* 11 * per_cpu/cluster helper 12 */ 13 struct per_cpu_reg { 14 int cluster_addr; 15 int cpu_stride; 16 }; 17 18 #define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \ 19 (cpu << reg[cluster].cpu_stride)) 20 #define per_cluster(cluster, reg) (reg[cluster].cluster_addr) 21 22 /* SPMC related registers */ 23 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000) 24 /* bit-fields of SPM_POWERON_CONFIG_EN */ 25 #define BCLK_CG_EN (1 << 0) 26 #define MD_BCLK_CG_EN (1 << 1) 27 #define PROJECT_CODE (0xb16 << 16) 28 29 #define SPM_PWR_STATUS (SPM_BASE + 0x180) 30 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184) 31 32 #define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4) 33 #define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8) 34 35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) 36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208) 37 #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) 38 #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210) 39 #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214) 40 #define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) 41 #define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) 42 #define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220) 43 #define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224) 44 #define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228) 45 #define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) 46 #define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) 47 #define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248) 48 #define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) 49 #define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250) 50 #define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254) 51 #define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) 52 #define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) 53 #define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260) 54 #define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264) 55 #define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268) 56 #define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) 57 58 #define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) 59 /* bit-fields of SPM_CPU_EXT_BUCK_ISO */ 60 #define MP0_EXT_BUCK_ISO (1 << 0) 61 #define MP1_EXT_BUCK_ISO (1 << 1) 62 #define MP_EXT_BUCK_ISO (1 << 2) 63 64 /* bit-fields of SPM_PWR_STATUS */ 65 #define PWR_STATUS_MD (1 << 0) 66 #define PWR_STATUS_CONN (1 << 1) 67 #define PWR_STATUS_DDRPHY (1 << 2) 68 #define PWR_STATUS_DISP (1 << 3) 69 #define PWR_STATUS_MFG (1 << 4) 70 #define PWR_STATUS_ISP (1 << 5) 71 #define PWR_STATUS_INFRA (1 << 6) 72 #define PWR_STATUS_VDEC (1 << 7) 73 #define PWR_STATUS_MP0_CPUTOP (1 << 8) 74 #define PWR_STATUS_MP0_CPU0 (1 << 9) 75 #define PWR_STATUS_MP0_CPU1 (1 << 10) 76 #define PWR_STATUS_MP0_CPU2 (1 << 11) 77 #define PWR_STATUS_MP0_CPU3 (1 << 12) 78 #define PWR_STATUS_MCUSYS (1 << 14) 79 #define PWR_STATUS_MP1_CPUTOP (1 << 15) 80 #define PWR_STATUS_MP1_CPU0 (1 << 16) 81 #define PWR_STATUS_MP1_CPU1 (1 << 17) 82 #define PWR_STATUS_MP1_CPU2 (1 << 18) 83 #define PWR_STATUS_MP1_CPU3 (1 << 19) 84 #define PWR_STATUS_VEN (1 << 21) 85 #define PWR_STATUS_MFG_ASYNC (1 << 23) 86 #define PWR_STATUS_AUDIO (1 << 24) 87 #define PWR_STATUS_C2K (1 << 28) 88 #define PWR_STATUS_MD_INFRA (1 << 29) 89 90 91 /* bit-fields of SPM_*_PWR_CON */ 92 #define PWRCTRL_PWR_RST_B (1 << 0) 93 #define PWRCTRL_PWR_ISO (1 << 1) 94 #define PWRCTRL_PWR_ON (1 << 2) 95 #define PWRCTRL_PWR_ON_2ND (1 << 3) 96 #define PWRCTRL_PWR_CLK_DIS (1 << 4) 97 #define PWRCTRL_PWR_SRAM_CKISO (1 << 5) 98 #define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6) 99 #define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7) 100 #define PWRCTRL_PWR_SRAM_PDN (1 << 8) 101 #define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12) 102 #define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24) 103 #define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28) 104 105 /* per_cpu registers for SPM_MP?_CPU?_PWR_CON */ 106 static const struct per_cpu_reg SPM_CPU_PWR[] = { 107 [0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 }, 108 [1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 }, 109 }; 110 111 /* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */ 112 static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { 113 [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON }, 114 [1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON }, 115 }; 116 117 /* APB Module infracfg_ao */ 118 #define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250) 119 #define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258) 120 #define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8) 121 #define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC) 122 123 /* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */ 124 #define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \ 125 (1 << 13)|(1 << 26)) 126 #define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \ 127 (1 << 15)|(1 << 27)) 128 129 /* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */ 130 #define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \ 131 (1 << 13)|(1 << 26)) 132 #define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \ 133 (1 << 15)|(1 << 27)) 134 135 136 /* 137 * MCU configuration registers 138 */ 139 140 /* bit-fields of MCUCFG_MP?_AXI_CONFIG */ 141 #define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0) 142 #define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1) 143 #define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2) 144 #define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3) 145 #define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4) 146 #define MCUCFG_AXI_CONFIG_AINACTS (1 << 5) 147 148 149 #define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2]) 150 #define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3]) 151 #define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2]) 152 #define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3]) 153 154 #define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00) 155 /* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */ 156 #define CPU0_SPARK_VRET_CTRL (0x3f << 0) 157 #define CPU1_SPARK_VRET_CTRL (0x3f << 8) 158 #define CPU2_SPARK_VRET_CTRL (0x3f << 16) 159 #define CPU3_SPARK_VRET_CTRL (0x3f << 24) 160 161 /* SPARK control in little cores */ 162 #define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30) 163 #define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34) 164 #define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38) 165 #define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c) 166 /* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */ 167 #define SW_SPARK_EN (1 << 0) 168 #define SW_NO_WAIT_Q (1 << 1) 169 170 /* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */ 171 #define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000) 172 #define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8) 173 /* bit-fields of MCUCFG_MP2_PWR_RST_CTL */ 174 #define SW_RST_B (1 << 0) 175 #define TOPAON_APB_MASK (1 << 1) 176 177 #define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208) 178 179 #define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290) 180 #define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298) 181 #define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0) 182 #define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8) 183 184 /* SPMC control */ 185 #define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788) 186 #define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0) 187 #define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC) 188 189 /* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */ 190 static const struct per_cpu_reg MCUCFG_BOOTADDR[] = { 191 [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 }, 192 }; 193 194 /* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */ 195 static const struct per_cpu_reg MCUCFG_INITARCH[] = { 196 [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 }, 197 [1] = { .cluster_addr = MCUCFG_MP2_CPUCFG }, 198 }; 199 200 /* SPARK control in BIG cores */ 201 #define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430) 202 #define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434) 203 #define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438) 204 #define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c) 205 #define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440) 206 #define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444) 207 #define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448) 208 #define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c) 209 /* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */ 210 #define SW_SPARK_EN (1 << 0) 211 #define SW_NO_WAIT_Q (1 << 1) 212 213 #define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700) 214 /* bit-fields of MCUCFG_MP2_SPARK2LDO */ 215 #define SPARK_VRET_CTRL (0x3f << 0) 216 #define CPU0_SPARK_LDO_AMUXSEL (0xf << 6) 217 #define CPU1_SPARK_LDO_AMUXSEL (0xf << 10) 218 #define CPU2_SPARK_LDO_AMUXSEL (0xf << 14) 219 #define CPU3_SPARK_LDO_AMUXSEL (0xf << 18) 220 221 /* per_cpu registers for SPARK */ 222 static const struct per_cpu_reg MCUCFG_SPARK[] = { 223 [0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 }, 224 [1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 }, 225 }; 226 227 /* per_cpu registers for SPARK2LDO */ 228 static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = { 229 [0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL }, 230 [1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO }, 231 }; 232 233 #endif /* MTSPMC_PRIVATE_H */ 234