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Searched refs:PreIndex (Results 1 – 25 of 39) sorted by relevance

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/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc1600 {{al, r0, r2, minus, 3194, PreIndex},
1610 {{al, r5, r6, plus, 1437, PreIndex},
1625 {{al, r5, r0, plus, 1066, PreIndex},
1630 {{al, r11, r6, minus, 3069, PreIndex},
1635 {{al, r12, r3, plus, 595, PreIndex},
1640 {{al, r7, r2, minus, 4093, PreIndex},
1645 {{al, r8, r7, plus, 1872, PreIndex},
1650 {{al, r0, r4, plus, 2792, PreIndex},
1655 {{al, r11, r6, minus, 2948, PreIndex},
1675 {{al, r0, r13, minus, 3397, PreIndex},
[all …]
Dtest-assembler-cond-rd-memop-immediate-512-a32.cc1610 {{al, r5, r3, minus, 99, PreIndex},
1620 {{al, r13, r12, plus, 161, PreIndex},
1625 {{al, r4, r13, minus, 132, PreIndex},
1635 {{al, r11, r14, minus, 116, PreIndex},
1645 {{al, r8, r4, minus, 198, PreIndex},
1655 {{al, r11, r3, minus, 107, PreIndex},
1670 {{al, r7, r6, plus, 83, PreIndex},
1680 {{al, r2, r1, minus, 124, PreIndex},
1690 {{al, r5, r4, minus, 138, PreIndex},
1700 {{al, r0, r2, plus, 57, PreIndex},
[all …]
Dtest-assembler-cond-rd-memop-rs-a32.cc1604 {{al, r2, r5, plus, r9, PreIndex},
1609 {{al, r8, r14, plus, r9, PreIndex},
1614 {{al, r2, r10, minus, r3, PreIndex},
1624 {{al, r1, r2, plus, r4, PreIndex},
1634 {{al, r1, r8, plus, r6, PreIndex},
1639 {{al, r13, r1, minus, r7, PreIndex},
1654 {{al, r10, r14, minus, r6, PreIndex},
1669 {{al, r8, r9, minus, r1, PreIndex},
1679 {{al, r7, r8, minus, r8, PreIndex},
1684 {{al, r5, r9, plus, r13, PreIndex},
[all …]
Dtest-simulator-cond-rd-memop-immediate-8192-a32.cc2328 {{al, r14, r12, plus, 2982, PreIndex},
2333 {{al, r7, r11, plus, 1241, PreIndex},
2338 {{al, r6, r5, plus, 2677, PreIndex},
2343 {{al, r11, r12, plus, 2403, PreIndex},
2348 {{al, r6, r5, plus, 1274, PreIndex},
2353 {{al, r6, r7, plus, 2208, PreIndex},
2358 {{al, r7, r10, plus, 3583, PreIndex},
2363 {{al, r7, r5, plus, 3975, PreIndex},
2368 {{al, r3, r9, plus, 2326, PreIndex},
2373 {{al, r8, r7, plus, 2098, PreIndex},
[all …]
Dtest-simulator-cond-rd-memop-immediate-512-a32.cc2328 {{al, r14, r9, plus, 41, PreIndex},
2333 {{al, r7, r9, plus, 78, PreIndex},
2338 {{al, r6, r3, plus, 255, PreIndex},
2343 {{al, r11, r8, plus, 139, PreIndex},
2348 {{al, r6, r3, plus, 170, PreIndex},
2353 {{al, r6, r4, plus, 221, PreIndex},
2358 {{al, r7, r8, plus, 229, PreIndex},
2363 {{al, r7, r4, plus, 18, PreIndex},
2368 {{al, r3, r8, plus, 157, PreIndex},
2373 {{al, r8, r5, plus, 82, PreIndex},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc1602 {{al, r8, r0, plus, r1, ASR, 3, PreIndex},
1607 {{al, r0, r14, minus, r6, ASR, 27, PreIndex},
1622 {{al, r2, r5, plus, r6, ASR, 7, PreIndex},
1632 {{al, r0, r11, minus, r1, ASR, 13, PreIndex},
1637 {{al, r13, r12, plus, r6, LSR, 16, PreIndex},
1642 {{al, r10, r2, plus, r10, LSR, 31, PreIndex},
1647 {{al, r14, r11, plus, r14, LSR, 9, PreIndex},
1652 {{al, r0, r2, minus, r12, LSR, 9, PreIndex},
1662 {{al, r7, r14, minus, r5, ASR, 21, PreIndex},
1682 {{al, r3, r4, minus, r9, LSR, 8, PreIndex},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc1602 {{al, r8, r3, minus, r4, ROR, 30, PreIndex},
1607 {{al, r1, r0, plus, r5, LSL, 13, PreIndex},
1622 {{al, r2, r6, plus, r7, ROR, 18, PreIndex},
1627 {{al, r0, r11, minus, r11, ROR, 26, PreIndex},
1632 {{al, r14, r4, plus, r14, LSL, 12, PreIndex},
1637 {{al, r10, r6, minus, r13, LSL, 15, PreIndex},
1642 {{al, r0, r2, minus, r13, ROR, 30, PreIndex},
1652 {{al, r8, r3, plus, r8, ROR, 26, PreIndex},
1672 {{al, r3, r6, plus, r8, LSL, 28, PreIndex},
1677 {{al, r9, r3, plus, r12, ROR, 21, PreIndex},
[all …]
Dtest-simulator-cond-rd-memop-rs-a32.cc2335 {{al, r12, r9, plus, r0, PreIndex},
2340 {{al, r0, r4, plus, r11, PreIndex},
2345 {{al, r14, r8, plus, r7, PreIndex},
2350 {{al, r2, r1, plus, r8, PreIndex},
2355 {{al, r7, r9, plus, r5, PreIndex},
2360 {{al, r11, r12, plus, r3, PreIndex},
2365 {{al, r8, r1, plus, r6, PreIndex},
2370 {{al, r9, r10, plus, r8, PreIndex},
2375 {{al, r12, r1, plus, r0, PreIndex},
2380 {{al, r10, r7, plus, r3, PreIndex},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc2333 {{al, r4, r9, plus, r3, LSL, 2, PreIndex},
2338 {{al, r1, r9, plus, r10, LSL, 25, PreIndex},
2343 {{al, r14, r1, plus, r12, ROR, 24, PreIndex},
2348 {{al, r3, r10, plus, r14, LSL, 24, PreIndex},
2353 {{al, r10, r5, plus, r0, LSL, 17, PreIndex},
2358 {{al, r1, r7, plus, r8, LSL, 20, PreIndex},
2363 {{al, r5, r6, plus, r2, LSL, 3, PreIndex},
2368 {{al, r4, r6, plus, r2, ROR, 9, PreIndex},
2373 {{al, r0, r11, plus, r12, LSL, 7, PreIndex},
2378 {{al, r2, r14, plus, r11, ROR, 4, PreIndex},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc2333 {{al, r4, r7, plus, r5, LSR, 28, PreIndex},
2338 {{al, r1, r9, plus, r0, LSR, 17, PreIndex},
2343 {{al, r12, r9, plus, r7, ASR, 17, PreIndex},
2348 {{al, r3, r9, plus, r6, LSR, 2, PreIndex},
2353 {{al, r10, r0, plus, r11, ASR, 9, PreIndex},
2358 {{al, r1, r6, plus, r12, ASR, 32, PreIndex},
2363 {{al, r5, r2, plus, r14, ASR, 15, PreIndex},
2368 {{al, r4, r3, plus, r7, LSR, 12, PreIndex},
2373 {{al, r0, r11, plus, r7, LSR, 3, PreIndex},
2378 {{al, r2, r12, plus, r8, ASR, 31, PreIndex},
[all …]
Dtest-disasm-a32.cc654 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PreIndex)), in TEST()
658 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PreIndex)), in TEST()
661 COMPARE_A32(Ldr(r0, MemOperand(r1, -0xff123, PreIndex)), in TEST()
665 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PreIndex)), in TEST()
669 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PreIndex)), in TEST()
672 COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PreIndex)), in TEST()
722 MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PreIndex)), in TEST()
755 COMPARE_T32(Ldr(r0, MemOperand(r1, minus, r2, PreIndex)), in TEST()
770 COMPARE_A32(Ldr(pc, MemOperand(r0, r0, PreIndex)), "ldr pc, [r0, r0]!\n"); in TEST()
771 COMPARE_T32(Ldr(pc, MemOperand(r0, r0, PreIndex)), in TEST()
[all …]
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc974 COMPARE(ldr(w0, MemOperand(x1, 4, PreIndex)), "ldr w0, [x1, #4]!"); in TEST()
975 COMPARE(ldr(w2, MemOperand(x3, 255, PreIndex)), "ldr w2, [x3, #255]!"); in TEST()
976 COMPARE(ldr(w4, MemOperand(x5, -256, PreIndex)), "ldr w4, [x5, #-256]!"); in TEST()
977 COMPARE(ldr(x6, MemOperand(x7, 8, PreIndex)), "ldr x6, [x7, #8]!"); in TEST()
978 COMPARE(ldr(x8, MemOperand(x9, 255, PreIndex)), "ldr x8, [x9, #255]!"); in TEST()
979 COMPARE(ldr(x10, MemOperand(x11, -256, PreIndex)), "ldr x10, [x11, #-256]!"); in TEST()
980 COMPARE(str(w12, MemOperand(x13, 4, PreIndex)), "str w12, [x13, #4]!"); in TEST()
981 COMPARE(str(w14, MemOperand(x15, 255, PreIndex)), "str w14, [x15, #255]!"); in TEST()
982 COMPARE(str(w16, MemOperand(x17, -256, PreIndex)), "str w16, [x17, #-256]!"); in TEST()
983 COMPARE(str(x18, MemOperand(x19, 8, PreIndex)), "str x18, [x19, #8]!"); in TEST()
[all …]
Dtest-disasm-neon-aarch64.cc89 COMPARE(ldr(s0, MemOperand(x1, 4, PreIndex)), "ldr s0, [x1, #4]!"); in TEST()
90 COMPARE(ldr(s2, MemOperand(x3, 255, PreIndex)), "ldr s2, [x3, #255]!"); in TEST()
91 COMPARE(ldr(s4, MemOperand(x5, -256, PreIndex)), "ldr s4, [x5, #-256]!"); in TEST()
92 COMPARE(ldr(d6, MemOperand(x7, 8, PreIndex)), "ldr d6, [x7, #8]!"); in TEST()
93 COMPARE(ldr(d8, MemOperand(x9, 255, PreIndex)), "ldr d8, [x9, #255]!"); in TEST()
94 COMPARE(ldr(d10, MemOperand(x11, -256, PreIndex)), "ldr d10, [x11, #-256]!"); in TEST()
96 COMPARE(str(s12, MemOperand(x13, 4, PreIndex)), "str s12, [x13, #4]!"); in TEST()
97 COMPARE(str(s14, MemOperand(x15, 255, PreIndex)), "str s14, [x15, #255]!"); in TEST()
98 COMPARE(str(s16, MemOperand(x17, -256, PreIndex)), "str s16, [x17, #-256]!"); in TEST()
99 COMPARE(str(d18, MemOperand(x19, 8, PreIndex)), "str d18, [x19, #8]!"); in TEST()
[all …]
Dtest-assembler-aarch64.cc2929 __ Ldr(w2, MemOperand(x26, 6144 * sizeof(src[0]), PreIndex)); in TEST()
2930 __ Str(w2, MemOperand(x27, 6144 * sizeof(dst[0]), PreIndex)); in TEST()
2971 __ Ldr(w0, MemOperand(x17, 4, PreIndex)); in TEST()
2972 __ Str(w0, MemOperand(x18, 12, PreIndex)); in TEST()
2973 __ Ldr(x1, MemOperand(x19, 8, PreIndex)); in TEST()
2974 __ Str(x1, MemOperand(x20, 16, PreIndex)); in TEST()
2975 __ Ldr(w2, MemOperand(x21, -4, PreIndex)); in TEST()
2976 __ Str(w2, MemOperand(x22, -4, PreIndex)); in TEST()
2977 __ Ldrb(w3, MemOperand(x23, 1, PreIndex)); in TEST()
2978 __ Strb(w3, MemOperand(x24, 25, PreIndex)); in TEST()
[all …]
Dtest-cpu-features-aarch64.cc288 TEST_NONE(ldpsw_2, ldpsw(x0, x1, MemOperand(x2, 104, PreIndex)))
291 TEST_NONE(ldp_2, ldp(w0, w1, MemOperand(x2, -252, PreIndex)))
294 TEST_NONE(ldp_5, ldp(x0, x1, MemOperand(x2, 360, PreIndex)))
296 TEST_NONE(ldrb_1, ldrb(w0, MemOperand(x1, -137, PreIndex)))
302 TEST_NONE(ldrh_1, ldrh(w0, MemOperand(x1, 52, PreIndex)))
307 TEST_NONE(ldrsb_1, ldrsb(w0, MemOperand(x1, -253, PreIndex)))
310 TEST_NONE(ldrsb_4, ldrsb(x0, MemOperand(x1, 11, PreIndex)))
319 TEST_NONE(ldrsh_1, ldrsh(w0, MemOperand(x1, -34, PreIndex)))
322 TEST_NONE(ldrsh_4, ldrsh(x0, MemOperand(x1, 72, PreIndex)))
329 TEST_NONE(ldrsw_1, ldrsw(x0, MemOperand(x1, 13, PreIndex)))
[all …]
Dtest-trace-aarch64.cc172 __ ldp(w23, w24, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
175 __ ldp(x25, x26, MemOperand(x1, 16, PreIndex)); in GenerateTestSequenceBase()
178 __ ldpsw(x27, x28, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
181 __ ldr(w29, MemOperand(x1, 4, PreIndex)); in GenerateTestSequenceBase()
184 __ ldr(x2, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
187 __ ldrb(w3, MemOperand(x1, 1, PreIndex)); in GenerateTestSequenceBase()
190 __ ldrb(x4, MemOperand(x1, 1, PreIndex)); in GenerateTestSequenceBase()
193 __ ldrh(w5, MemOperand(x1, 2, PreIndex)); in GenerateTestSequenceBase()
196 __ ldrh(x6, MemOperand(x1, 2, PreIndex)); in GenerateTestSequenceBase()
199 __ ldrsb(w7, MemOperand(x1, 1, PreIndex)); in GenerateTestSequenceBase()
[all …]
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.cc1723 case PreIndex: in Delegate()
1739 MemOperand(rn, load_store_offset, PreIndex)); in Delegate()
1816 case PreIndex: in Delegate()
1945 case PreIndex: { in Delegate()
1966 MemOperand(rn, load_store_offset, PreIndex)); in Delegate()
2025 case PreIndex: in Delegate()
2110 case PreIndex: in Delegate()
2183 case PreIndex: in Delegate()
Doperands-aarch32.h829 bool IsPreIndex() const { return GetAddrMode() == PreIndex; } in IsPreIndex()
879 VIXL_ASSERT(addrmode != PreIndex); in MemOperand()
887 VIXL_ASSERT(addrmode != PreIndex); in AlignedMemOperand()
Doperands-aarch32.cc544 } else if (operand.GetAddrMode() == PreIndex) { in operator <<()
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc2108 Stp(bottom_0, bottom_1, MemOperand(StackPointer(), -size, PreIndex)); in PushCPURegList()
2110 Str(bottom_0, MemOperand(StackPointer(), -size, PreIndex)); in PushCPURegList()
2205 str(src0, MemOperand(StackPointer(), -1 * size, PreIndex)); in PushHelper()
2209 stp(src1, src0, MemOperand(StackPointer(), -2 * size, PreIndex)); in PushHelper()
2213 stp(src2, src1, MemOperand(StackPointer(), -3 * size, PreIndex)); in PushHelper()
2220 stp(src3, src2, MemOperand(StackPointer(), -4 * size, PreIndex)); in PushHelper()
2368 MemOperand tos(sp, -2 * static_cast<int>(kXRegSizeInBytes), PreIndex); in PushCalleeSavedRegisters()
Doperands-aarch64.cc364 bool MemOperand::IsPreIndex() const { return addrmode_ == PreIndex; } in IsPreIndex()
Dinstructions-aarch64.h175 enum AddrMode { Offset, PreIndex, PostIndex }; enumerator
Doperands-aarch64.h445 ((addrmode_ == Offset) || (addrmode_ == PreIndex) || in IsValid()
/external/vixl/benchmarks/aarch64/
Dbench-utils.cc261 __ Ldrsw(PickX(), MemOperand(scratch, -42, PreIndex)); in GenerateMemOperandSequence()
/external/swiftshader/third_party/subzero/src/
DIceInstARM32.h91 PreIndex = (8 | 4 | 1) << 21, // pre-indexed addressing with writeback enumerator
130 static_assert((PreIndex & (4 << 21)) != 0, in isNegAddrMode()

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