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Searched refs:Proc (Results 1 – 25 of 133) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Sparc/
DSparc.td87 class Proc<string Name, list<SubtargetFeature> Features>
90 def : Proc<"generic", []>;
91 def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>;
92 def : Proc<"v8", []>;
93 def : Proc<"supersparc", []>;
94 def : Proc<"sparclite", []>;
95 def : Proc<"f934", []>;
96 def : Proc<"hypersparc", []>;
97 def : Proc<"sparclite86x", []>;
98 def : Proc<"sparclet", []>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparc.td87 class Proc<string Name, list<SubtargetFeature> Features>
90 def : Proc<"generic", []>;
91 def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>;
92 def : Proc<"v8", []>;
93 def : Proc<"supersparc", []>;
94 def : Proc<"sparclite", []>;
95 def : Proc<"f934", []>;
96 def : Proc<"hypersparc", []>;
97 def : Proc<"sparclite86x", []>;
98 def : Proc<"sparclet", []>;
[all …]
/external/llvm/lib/Target/AMDGPU/
DProcessors.td10 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
16 def : Proc<"r600", R600_VLIW5_Itin,
19 def : Proc<"r630", R600_VLIW5_Itin,
22 def : Proc<"rs880", R600_VLIW5_Itin,
25 def : Proc<"rv670", R600_VLIW5_Itin,
32 def : Proc<"rv710", R600_VLIW5_Itin,
35 def : Proc<"rv730", R600_VLIW5_Itin,
38 def : Proc<"rv770", R600_VLIW5_Itin,
45 def : Proc<"cedar", R600_VLIW5_Itin,
49 def : Proc<"redwood", R600_VLIW5_Itin,
[all …]
/external/llvm/lib/Target/Sparc/
DSparc.td71 class Proc<string Name, list<SubtargetFeature> Features>
74 def : Proc<"generic", []>;
75 def : Proc<"v7", []>;
76 def : Proc<"v8", []>;
77 def : Proc<"supersparc", []>;
78 def : Proc<"sparclite", []>;
79 def : Proc<"f934", []>;
80 def : Proc<"hypersparc", []>;
81 def : Proc<"sparclite86x", []>;
82 def : Proc<"sparclet", []>;
[all …]
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTX.td91 class Proc<string Name, list<SubtargetFeature> Features>
94 def : Proc<"sm_20", [SM20]>;
95 def : Proc<"sm_21", [SM21]>;
96 def : Proc<"sm_30", [SM30]>;
97 def : Proc<"sm_32", [SM32, PTX40]>;
98 def : Proc<"sm_35", [SM35]>;
99 def : Proc<"sm_37", [SM37, PTX41]>;
100 def : Proc<"sm_50", [SM50, PTX40]>;
101 def : Proc<"sm_52", [SM52, PTX41]>;
102 def : Proc<"sm_53", [SM53, PTX42]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTX.td85 class Proc<string Name, list<SubtargetFeature> Features>
88 def : Proc<"sm_20", [SM20]>;
89 def : Proc<"sm_21", [SM21]>;
90 def : Proc<"sm_30", [SM30]>;
91 def : Proc<"sm_32", [SM32, PTX40]>;
92 def : Proc<"sm_35", [SM35]>;
93 def : Proc<"sm_37", [SM37, PTX41]>;
94 def : Proc<"sm_50", [SM50, PTX40]>;
95 def : Proc<"sm_52", [SM52, PTX41]>;
96 def : Proc<"sm_53", [SM53, PTX42]>;
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTX.td72 class Proc<string Name, list<SubtargetFeature> Features>
75 def : Proc<"sm_20", [SM20]>;
76 def : Proc<"sm_21", [SM21]>;
77 def : Proc<"sm_30", [SM30]>;
78 def : Proc<"sm_32", [SM32, PTX40]>;
79 def : Proc<"sm_35", [SM35]>;
80 def : Proc<"sm_37", [SM37, PTX41]>;
81 def : Proc<"sm_50", [SM50, PTX40]>;
82 def : Proc<"sm_52", [SM52, PTX41]>;
83 def : Proc<"sm_53", [SM53, PTX42]>;
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/external/llvm-project/llvm/test/tools/llvm-readobj/ELF/
Dmips-options-sec.test12 # CHECK-NEXT: Co-Proc Mask0: 0x88776655
13 # CHECK-NEXT: Co-Proc Mask1: 0xCCBBAA99
14 # CHECK-NEXT: Co-Proc Mask2: 0x1EFFEEDD
15 # CHECK-NEXT: Co-Proc Mask3: 0x5E4E3E2E
20 # CHECK-NEXT: Co-Proc Mask0: 0x0
21 # CHECK-NEXT: Co-Proc Mask1: 0x0
22 # CHECK-NEXT: Co-Proc Mask2: 0x0
23 # CHECK-NEXT: Co-Proc Mask3: 0x0
40 # NAME-ERR-FOUND-NEXT: Co-Proc Mask0: 0x88776655
41 # NAME-ERR-FOUND-NEXT: Co-Proc Mask1: 0xCCBBAA99
[all …]
/external/llvm/lib/Target/Mips/
DMips.td190 class Proc<string Name, list<SubtargetFeature> Features>
193 def : Proc<"mips1", [FeatureMips1]>;
194 def : Proc<"mips2", [FeatureMips2]>;
195 def : Proc<"mips32", [FeatureMips32]>;
196 def : Proc<"mips32r2", [FeatureMips32r2]>;
197 def : Proc<"mips32r3", [FeatureMips32r3]>;
198 def : Proc<"mips32r5", [FeatureMips32r5]>;
199 def : Proc<"mips32r6", [FeatureMips32r6]>;
201 def : Proc<"mips3", [FeatureMips3]>;
202 def : Proc<"mips4", [FeatureMips4]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPF.td17 class Proc<string Name, list<SubtargetFeature> Features>
20 def : Proc<"generic", []>;
21 def : Proc<"v1", []>;
22 def : Proc<"v2", []>;
23 def : Proc<"v3", []>;
24 def : Proc<"probe", []>;
/external/llvm-project/llvm/lib/Target/BPF/
DBPF.td17 class Proc<string Name, list<SubtargetFeature> Features>
20 def : Proc<"generic", []>;
21 def : Proc<"v1", []>;
22 def : Proc<"v2", []>;
23 def : Proc<"v3", []>;
24 def : Proc<"probe", []>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips.td232 class Proc<string Name, list<SubtargetFeature> Features>
235 def : Proc<"generic", [FeatureMips32]>;
236 def : Proc<"mips1", [FeatureMips1]>;
237 def : Proc<"mips2", [FeatureMips2]>;
238 def : Proc<"mips32", [FeatureMips32]>;
239 def : Proc<"mips32r2", [FeatureMips32r2]>;
240 def : Proc<"mips32r3", [FeatureMips32r3]>;
241 def : Proc<"mips32r5", [FeatureMips32r5]>;
242 def : Proc<"mips32r6", [FeatureMips32r6]>;
244 def : Proc<"mips3", [FeatureMips3]>;
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMips.td235 class Proc<string Name, list<SubtargetFeature> Features>
238 def : Proc<"generic", [FeatureMips32]>;
239 def : Proc<"mips1", [FeatureMips1]>;
240 def : Proc<"mips2", [FeatureMips2]>;
241 def : Proc<"mips32", [FeatureMips32]>;
242 def : Proc<"mips32r2", [FeatureMips32r2]>;
243 def : Proc<"mips32r3", [FeatureMips32r3]>;
244 def : Proc<"mips32r5", [FeatureMips32r5]>;
245 def : Proc<"mips32r6", [FeatureMips32r6]>;
247 def : Proc<"mips3", [FeatureMips3]>;
[all …]
/external/llvm/lib/Target/X86/
DX86.td264 class Proc<string Name, list<SubtargetFeature> Features>
267 def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>;
268 def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>;
269 def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>;
270 def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
271 def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
272 def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
273 def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>;
274 def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
275 def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
[all …]
/external/llvm/test/tools/llvm-readobj/
Dmips-reginfo.test6 CHECK-NEXT: Co-Proc Mask0: 0x0
7 CHECK-NEXT: Co-Proc Mask1: 0x0
8 CHECK-NEXT: Co-Proc Mask2: 0x0
9 CHECK-NEXT: Co-Proc Mask3: 0x0
Dmips-options-sec.test7 CHECK-NEXT: Co-Proc Mask0: 0x0
8 CHECK-NEXT: Co-Proc Mask1: 0x0
9 CHECK-NEXT: Co-Proc Mask2: 0x0
10 CHECK-NEXT: Co-Proc Mask3: 0x0
/external/llvm-project/llvm/unittests/DebugInfo/CodeView/
DTypeHashingTest.cpp84 TypeIndex Proc[2]; in TEST() local
105 Proc[0] = createProcedureRecord(Ordering1, 2, IntPP[0], Args[0]); in TEST()
111 ASSERT_EQ(0x1004U, Proc[0].getIndex()); in TEST()
136 Proc[1] = createProcedureRecord(Ordering2, 2, IntPP[1], Args[1]); in TEST()
144 ASSERT_EQ(0x1005U, Proc[1].getIndex()); in TEST()
155 EXPECT_EQ(hash_of(Hashes1, Proc[0]), hash_of(Hashes2, Proc[1])); in TEST()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/PDB/Native/
DNativeTypeFunctionSig.cpp79 codeview::ProcedureRecord Proc) in NativeTypeFunctionSig() argument
81 Proc(std::move(Proc)), Index(Index), IsMemberFunction(false) {} in NativeTypeFunctionSig()
95 initializeArgList(Proc.ArgumentList); in initialize()
152 return IsMemberFunction ? MemberFunc.CallConv : Proc.CallConv; in getCallingConvention()
157 : Proc.getParameterCount(); in getCount()
162 IsMemberFunction ? MemberFunc.getReturnType() : Proc.getReturnType(); in getTypeId()
193 IsMemberFunction ? MemberFunc.getOptions() : Proc.getOptions(); in isCxxReturnUdt()
/external/llvm-project/llvm/lib/DebugInfo/PDB/Native/
DNativeTypeFunctionSig.cpp79 codeview::ProcedureRecord Proc) in NativeTypeFunctionSig() argument
81 Proc(std::move(Proc)), Index(Index), IsMemberFunction(false) {} in NativeTypeFunctionSig()
95 initializeArgList(Proc.ArgumentList); in initialize()
152 return IsMemberFunction ? MemberFunc.CallConv : Proc.CallConv; in getCallingConvention()
157 : Proc.getParameterCount(); in getCount()
162 IsMemberFunction ? MemberFunc.getReturnType() : Proc.getReturnType(); in getTypeId()
193 IsMemberFunction ? MemberFunc.getOptions() : Proc.getOptions(); in isCxxReturnUdt()
/external/skqp/bench/
DRegionContainBench.cpp20 typedef bool (*Proc)(SkRegion& a, SkRegion& b); typedef in RegionContainBench
22 Proc fProc;
36 RegionContainBench(Proc proc, const char name[]) { in RegionContainBench()
56 Proc proc = fProc; in onDraw()
/external/skia/bench/
DRegionContainBench.cpp20 typedef bool (*Proc)(SkRegion& a, SkRegion& b); typedef in RegionContainBench
22 Proc fProc;
36 RegionContainBench(Proc proc, const char name[]) { in RegionContainBench()
56 Proc proc = fProc; in onDraw()
/external/llvm-project/lld/test/ELF/
Dmips-reginfo.s21 # CHECK-NEXT: Co-Proc Mask0: 0x0
22 # CHECK-NEXT: Co-Proc Mask1: 0x0
23 # CHECK-NEXT: Co-Proc Mask2: 0x0
24 # CHECK-NEXT: Co-Proc Mask3: 0x0
Dmips-options.s38 # CHECK-NEXT: Co-Proc Mask0: 0x0
39 # CHECK-NEXT: Co-Proc Mask1: 0x0
40 # CHECK-NEXT: Co-Proc Mask2: 0x0
41 # CHECK-NEXT: Co-Proc Mask3: 0x0
/external/llvm-project/clang/lib/Basic/
DTargetID.cpp20 llvm::StringRef Proc) { in getAllPossibleAMDGPUTargetIDFeatures() argument
23 auto ProcKind = T.isAMDGCN() ? llvm::AMDGPU::parseArchAMDGCN(Proc) in getAllPossibleAMDGPUTargetIDFeatures()
24 : llvm::AMDGPU::parseArchR600(Proc); in getAllPossibleAMDGPUTargetIDFeatures()
153 llvm::StringRef Proc = in getConflictTargetIDCombination() local
155 auto Loc = FeatureMap.find(Proc); in getConflictTargetIDCombination()
157 FeatureMap[Proc] = Info{ID, Features}; in getConflictTargetIDCombination()
/external/llvm-project/llvm/lib/DebugInfo/CodeView/
DSymbolRecordHelpers.cpp32 ProcSym Proc = createRecord<ProcSym>(Sym); in getScopeEndOffset() local
33 return Proc.End; in getScopeEndOffset()
63 ProcSym Proc = createRecord<ProcSym>(Sym); in getScopeParentOffset() local
64 return Proc.Parent; in getScopeParentOffset()

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