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Searched refs:PtrReg (Results 1 – 18 of 18) sorted by relevance

/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp524 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
525 lowerParameterPtr(PtrReg, B, ParamTy, Offset); in lowerParameter()
533 B.buildLoad(DstReg, PtrReg, *MMO); in lowerParameter()
641 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
642 lowerParameterPtr(PtrReg, B, ArgTy, ArgOffset); in lowerFormalArgumentsKernel()
644 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
DAMDGPURegisterBankInfo.cpp1170 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1182 auto Load0 = B.buildLoadFromOffset(Part64, PtrReg, *MMO, 0); in applyMappingLoad()
1183 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8); in applyMappingLoad()
1190 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0); in applyMappingLoad()
3308 Register PtrReg) const { in getValueMappingForPtr()
3309 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
3317 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3328 Register PtrReg = MI.getOperand(1).getReg(); in getInstrMappingForLoad() local
3329 LLT PtrTy = MRI.getType(PtrReg); in getInstrMappingForLoad()
3336 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getInstrMappingForLoad()
DAMDGPULegalizerInfo.cpp2370 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
2371 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
2376 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
2417 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2425 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2433 B.buildLoadFromOffset(WideLoad, PtrReg, *MMO, 0); in legalizeLoad()
2469 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
2473 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
2483 .addUse(PtrReg) in legalizeAtomicCmpXChg()
DAMDGPUInstructionSelector.cpp2353 Register PtrReg = MI.getOperand(1).getReg(); in selectG_AMDGPU_ATOMIC_CMPXCHG() local
2354 const LLT PtrTy = MRI->getType(PtrReg); in selectG_AMDGPU_ATOMIC_CMPXCHG()
3358 unsigned PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm() local
3360 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm()
3374 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
3381 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
3408 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdSgpr() local
3413 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdSgpr()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp2152 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2160 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2162 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2165 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2170 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2177 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2182 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
2185 LHS = PtrReg.first; in applyCombineAddP2IToPtrAdd()
DLegalizerHelper.cpp961 Register PtrReg = MI.getOperand(1).getReg(); in narrowScalar() local
966 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
968 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); in narrowScalar()
2649 Register PtrReg = MI.getOperand(1).getReg(); in lowerLoad() local
2682 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
2688 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO); in lowerLoad()
2694 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lowerLoad()
2706 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); in lowerLoad()
2714 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in lowerLoad()
2745 Register PtrReg = MI.getOperand(1).getReg(); in lowerStore() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp815 Register PtrReg = MI.getOperand(1).getReg(); in narrowScalar() local
820 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
826 .addUse(PtrReg) in narrowScalar()
2075 Register PtrReg = MI.getOperand(1).getReg(); in lower() local
2108 LLT PtrTy = MRI.getType(PtrReg); in lower()
2114 MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO); in lower()
2120 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lower()
2131 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); in lower()
2139 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in lower()
2167 Register PtrReg = MI.getOperand(1).getReg(); in lower() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp373 Register PtrReg = lowerParameterPtr(B, ParamTy, Offset); in lowerParameter() local
381 B.buildLoad(DstReg, PtrReg, *MMO); in lowerParameter()
DAMDGPUInstructionSelector.cpp1984 unsigned PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm() local
1987 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm()
2001 unsigned PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
2007 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
2033 unsigned PtrReg = GEPInfo.SgprParts[0]; in selectSmrdSgpr() local
2038 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdSgpr()
DAMDGPULegalizerInfo.cpp1782 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
1787 MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
1798 .addUse(PtrReg) in legalizeAtomicCmpXChg()
DAMDGPURegisterBankInfo.cpp2356 Register PtrReg = MI.getOperand(1).getReg(); in getInstrMappingForLoad() local
2357 LLT PtrTy = MRI.getType(PtrReg); in getInstrMappingForLoad()
2364 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getInstrMappingForLoad()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp1840 const Register PtrReg = I.getOperand(1).getReg(); in select() local
1842 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
1846 assert(MRI.getType(PtrReg).isPointer() && in select()
1861 auto *PtrMI = MRI.getVRegDef(PtrReg); in select()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp8541 unsigned PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8591 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
8594 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
8609 .addReg(ZeroReg).addReg(PtrReg); in EmitPartwordAtomicBinary()
8620 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); in EmitPartwordAtomicBinary()
9256 unsigned PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
9316 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
9319 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
9341 .addReg(ZeroReg).addReg(PtrReg); in EmitInstrWithCustomInserter()
9357 .addReg(ZeroReg).addReg(PtrReg); in EmitInstrWithCustomInserter()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp10782 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
10842 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
10847 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
10868 .addReg(PtrReg); in EmitPartwordAtomicBinary()
10912 .addReg(PtrReg); in EmitPartwordAtomicBinary()
11593 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
11663 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
11668 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
11700 .addReg(PtrReg); in EmitInstrWithCustomInserter()
11724 .addReg(PtrReg); in EmitInstrWithCustomInserter()
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp11374 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
11434 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
11439 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
11460 .addReg(PtrReg); in EmitPartwordAtomicBinary()
11504 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12371 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
12441 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
12446 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
12478 .addReg(PtrReg); in EmitInstrWithCustomInserter()
12502 .addReg(PtrReg); in EmitInstrWithCustomInserter()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp2557 const Register PtrReg = I.getOperand(1).getReg(); in select() local
2558 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2562 assert(MRI.getType(PtrReg).isPointer() && in select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp4456 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
4457 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp4608 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
4609 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()